• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.94-100
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• 2017

Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (${\Delta}L_{ch}$) and threshold voltage shift (${\Delta}V_{th}$). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2001.11b
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• pp.1376-1383
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• 2001

Modem technology depends on the reliability of extremely high technology equipments. In the production of semiconductor wafer, optical and electron microscopes, ion-beam, laser device must maintain their alignments within a sub-micrometer. This equipment requires a vibration free environment to provide its proper function. Especially, lithography and inspection devices, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved giga and tera class semiconductor wafers. This high technology equipments require very strict environmental vibration standard, vibration criteria, in proportion to the accuracy of the manufacturing, inspecting devices. The vibration criteria of high sensitive equipment should be represented in the form of 'exactness' and 'accuracy', because this is used as basic data for the design of building structure and structural dynamics of equipment. This paper deals with the properties of time and frequency domain in order to obtain more improved vibration criteria for high sensitive equipment.

• Electronics and Telecommunications Trends
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• v.35 no.4
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• pp.1-10
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• 2020

Since the 1960s, semiconductor packaging technology has developed into electrical joining techniques using lead frames or C4 bumps using tin-lead solder compositions based on traditional reflow processes. To meet the demands of a highly integrated semiconductor device, high reliability, high productivity, and an eco-friendly simplified process, packaging technology was required to use new materials and processes such as lead-free solder, epoxy-based non cleaning interconnection material, and laser based high-speed processes. For next generation semiconductor packaging, the study status of two epoxy-based interconnection materials such as fluxing and hybrid underfills along with a laser-assisted bonding process were introduced for fine pitch semiconductor applications. The fluxing underfill is a solvent-free and non-washing epoxy-based material, which combines the underfill role and fluxing function of the Surface Mounting Technology (SMT) process. The hybrid underfill is a mixture of the above fluxing underfill and lead-free solder powder. For low-heat-resistant substrate applications such as polyethylene terephthalate (PET) and high productivity, laser-assisted bonding technology is introduced with two epoxy-based underfill materials. Fluxing and hybrid underfills as next-generation semiconductor packaging materials along with laser-assisted bonding as a new process are expected to play an active role in next-generation large displays and Augmented Reality (AR) and Virtual Reality (VR) markets.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.450-450
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• 2012

In recent days, advances in ZnO-based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). In particular, the development of high-mobility ZnO-based channel materials has been proven invaluable; thus, there have been many reports of high-performance TFTs with oxide semiconductor channels such as ZnO, InZnO (IZO), ZnSnO (ZTO), and InGaZnO (IGZO). The reliability of oxide TFTs can be improved by examining more stable oxide channel materials. In the present study, we investigated the effects of an ALD-deposited water vapor permeation barrier on the stability of ZnO and HfZnO (HZO) thin film transistors. The device without the water vapor barrier films showed a large turn-on voltage shift under negative bias temperature stress. On the other hand, the suitably protected device with the lowest water vapor transmission rate showed a dramatically improved device performance. As the value of the water vapor transmission rate of the barrier films was decreased, the turn-on voltage instability reduced. The results suggest that water vapor related traps are strongly related to the instability of ZnO and HfZnO TFTs and that a proper combination of water vapor permeation barriers plays an important role in suppressing the device instability.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.182-187
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• 2015

In the three-phase power system, when any one-phase or two-phases is open-phase, the unbalanced current flows and the single-phase power supplies to three-phase loads. Specially, motor coil and transformer coil receive over-current. As a result, great damage as well as electrical fire can occur to the power system. In order to improve these problems, this paper proposes that an open-phase detection device is designed by a new algorithm using electric potential difference between the resultant voltage of neutral point and ground, and a control circuit topology of open-phase protector is composed of highly efficient semiconductor devices. It improves response speed and reliability. The control algorithm circuit also operates the cut-off of a conventional residual current protective device (RCD) which flows an enforced leakage current to ground wire at open-phase accident. Furthermore, time delay circuit is added to prevent the incapable operation of open-phase protector about instantaneous open-phase not open-phase fault. The time delay circuit improves more reliability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.3
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• pp.264-268
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• 2022

High pressure deuterium (HPD) annealing is an advancing technology for the fabrication of modern semiconductor devices. In this work, gate-enclosed FETs are fabricated on a silicon substrate as test vehicles. After a cycle for the HPD annealing, the device parameters such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), off-state current (I_OFF), and gate leakage (I_G) were measured and compared depending on the HPD. The HPD annealing can passivate the dangling bonds at Si-SiO₂ interfaces as well as eliminate the bulk trap in SiO₂. It can be concluded that adding the HPD annealing as a fabrication process is very effective in improving device reliability, performance, and variability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.519-522
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• 2001

Recently, the battery charging technology and reducing technology of harmonics on AC input line are rising importantly according to increasing electrical facilities that it has been replaced battery with emergency power. In this study, I proposed that an auto-charging circuit of battery has low cost with simple-construction circuit, relative, harmonics reduction with diode tap-change method, high reliability of system for using characteristics of thyristor switching. In case of this circuit, convenience and reliability of maintenance of battery power units were more improved. 1 think that it is resulted in effect of prevention to shortening of battery life from over-charging and over-discharging and decrease of harmonics obstacle on AC input line.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.139-144
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• 2013

Negative bias temperature instability (NBTI) has become a major factor determining circuit reliability. The effect of the NBTI on the circuit performance depends on the duty cycle which represents the stress and recovery conditions of each device in a circuit. In this paper, we propose an analytical model to perform more accurate duty cycle estimation at the gate-level. The proposed model allows accurate (average error rate: 3%) computation of the duty cycle without the need for expensive transistor-level simulations Furthermore, our model estimates the waveforms at each node, allowing various aging effects to be applied for a reliable gate-level circuit aging analysis framework.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.1
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• pp.1-6
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• 2002

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.204-209
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• 2017

We have investigated a Mo/Au gate scheme for use in AlGaN/GaN-on-Si HFETs. AlGaN/GaN-on-Si HFETs were fabricated with Ni/Au or Mo/Au gates and their electrical characteristics were compared after thermal stress tests. While insignificant difference was observed in DC characteristics, the Mo/Au gate device exhibited lower on-resistance with superior pulsed characteristics in comparison with the Ni/Au gate device.