• Proceedings of the Materials Research Society of Korea Conference
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• 2001.05a
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• pp.91-91
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• 2001

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.622-634
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• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.496-500
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• 1996

An air flow measurement device is proposed. The thermal characteristic of a semiconductor element is adopted as a cooling parameter of thermal convection rate. The difference between forced convection and natural convection of two Zener diodes results enough difference in temperature. Experiment at various air flow conditions shows the measuring capability of the air flow in a duct. This measuring device has some merits, such as a reliability n hard field condition, simple circuit for signal processing, small volume of the element, less air flow resistance, independance of various ai temperature. The experimental result shows that it is an exact and usefull air flow measurement device.

• Journal of Applied Reliability
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• v.10 no.1
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• Journal of the Korean Ceramic Society
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• v.41 no.4
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• pp.273-276
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• 2004

Report ferroelectric memories based on 0.35$\mu\textrm{m}$ CMOS technology ensuring ten-year retention and imprint at 175$^{\circ}C$. This excellent reliability resulted from newly developed BT-based ferroelectric films with superior reliability performance at high temperatures, and also resulted from robust integration schemes free from ferroelectric degradation due to process impurities such as moisture and hydrogen. The superior reliabilities at high temperature of ferroelectric memories using BT-based films are due to the random orientation by special bake treatments.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.138-142
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• 2019

As the NAND flash memory goes to 3D vertical Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structure, the lateral charge migration can be critical in the reliability performance. Even more, with miniaturization of flash memory cell device, just a little movement of trapped charge can cause reliability problems. In this paper, we propose a method of predicting the trapped charge profile in the retention mode. Charge diffusivity in the charge trapping layer (Si₃N₄) was extracted experimentally, and the effect on the trapped charge profile was demonstrated by the simulation and experiment.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.119-124
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• 2021

Along with the needs for feasibility in the field of space applications, interests in radiation-hardened electronics is growing rapidly. Gallium nitride (GaN)-based devices have been widely researched so far owing to superb radiation resistance. Among them, research on the most abundant protons in low earth orbit (LEO) is essential. In this paper, proton irradiation effects on parameter changes, degradation mechanism, and correlation with reliability of GaN-based devices are summarized.

• International Journal of Precision Engineering and Manufacturing
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• v.8 no.3
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• pp.50-53
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• 2007

Improving the reliability or long-term dependability of a system requires a different approach from the previous emphasis on short-term concerns. The purpose of this paper is to present a reliability evaluation method for an oil cooler intended for high-precision machining centers. The oil cooler system in question is a cooling device that minimizes the deformation caused from the heat generated by driving devices. This system is used for machine tools and semiconductor equipment. We predicted the reliability of the system based on the failure rate database and conducted the reliability test using a test-bed to evaluate the life of the oil cooler. The results provided an indication of the reliability of the system in terms of the failure rate and the MTBF of the oil cooler system and its components, as well as a distribution of the failure mode. These results will help increase the reliability of oil cooler systems. The evaluation method can also be used to determine the reliability of other machinery products.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.121-129
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• 2011

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.