• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.167-171
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• 2014

While the development of a portable plate panel display, thinning, high color reproduction, high brightness studies have been actively performed. LED, OLED is used as a light source. The research on quantum dot is much accomplished by the material of light source. Such quantum dot is the next generation semiconductor nano fluorescent substance because quantum dot has the high color reproduction and flexible display characteristic. In this study, we presented to method of using the quantum dot for implementation of the plate panel display. Quantum Dot (CdSe/ZnS), having a 100um thickness, is spread in PET barrier film. A Blue LED having a wavelength of 455nm as a light source irradiating light to the optical characteristic of the devices produced and evaluated. Also we presented the possibility for application with the color change film of the LCD.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.3
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• pp.221-233
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• 2007

In this paper, a simple but effective position profile generation algorithm for single axis high dynamic linear machine drive system is presented. In the recent industrial application fields like as LCD/PDP and semiconductor factory, requirements for the high performance positioning system with optimal position profile generator are highly increased to reduce the overall processing time. There might be various solutions for position profile generating algorithm according to the application type. A square-wave Impact quantity(Jerk) based algorithm with minimal locomotion time is argued in this paper to minimize the total time of one movement under some specific constrains such as maximum speed limit and maximum acceleration limit. In order to reduce the calculation efforts and satisfy the minimal locomotion time condition, the time variants representing each profile sector and a simple condition comparison algorithm are adopted. Also, the actual implementation method for profile generation algorithm and it's real performance results are presented through commercial linear machine drive system.

• Journal of the Korea Society for Simulation
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• v.25 no.1
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• pp.45-52
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• 2016

In this study, we consider a capacity planning problem of reentrant hybrid flowshops. High-tech electronic products such as semiconductor or TFT-LCD, are produced from manufacturing systems which can be considered as reentrant hybrid flowshops. In the considered capacity planning problem, we determine the number of machines at each stage in the manufacturing system. We introduce criteria indicating which stage needs additional machines or which stage needs reduction of machines considering the characteristics of the product types and the manufacturing system. The objective function of the problem is maximizing throughput rate of the system, of which values are obtained from the simulation model depicting the hybrid flowshops. The performance of the proposed methods were evaluated through a series of computational experiments. The simulation model was also used for conducting the comparison experiments among the proposed method and benchmarks.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.473-479
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• 2011

In this paper, we have compared amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) with the nano-crystalline embedded-IGZO ($N_c$-embedded-IGZO) TFT fabricated by solid-phase crystallization (SPC) technique. The field effect mobility (${\mu}_{FE}$) of $N_c$-embedded-IGZO TFT was 2.37 $cm^2/Vs$ and the subthreshold slope (S-factor) was 0.83 V/decade, which showed lower performance than those of a-IGZO TFT (${\mu}_{FE}$ of a-IGZO was 9.67 $cm^2/Vs$ and S-factor was 0.19 V/decade). This results originated from generation of oxygen vacancies in oxide semiconductor and interface between gate insulator and semiconductor due to high temperature annealing process. However, the threshold voltage shift (${\Delta}V_{TH}$) of $N_c$-embedded-IGZO TFT was 0.5 V, which showed 1 V less shift than that of a-IGZO TFT under constant current stress during $10^5$ s. This was because there were additionally less increase of interface trap charges in Nc-embedded-IGZO TFT than a-IGZO TFT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.15-22
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• 2005

This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.186-186
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• 2000

After LeComber et al. reported the first amorphous hydrogenated silicon (a-Si: H) TFT, many laboratories started the development of an active matrix LCDs using a-Si:H TFTs formed on glass substrate. With increasing the display area and pixel density of TFT-LCD, however, high mobility TFTs are required for pixel driver of TF-LCD in order to shorten the charging time of the pixel electrodes. The most important of these drawbacks is a-Si's electron mobiliy, which is the speed at which electrons can move through each transistor. The problem of low carier mobility for the a-Si:H TFTs can be overcome by introducing polycrystalline silicon (poly-Si) thin film instead of a-Si:H as a semiconductor layer of TFTs. Therefore, poly-Si has gained increasing interest and has been investigated by many researchers. Recnetly, fabrication of such poly-Si TFT-LCD panels with VGA pixel size and monolithic drivers has been reported, . Especially, fabricating poly-Si TFTs at a temperature mach lower than the strain point of glass is needed in order to have high mobility TFTs on large-size glass substrate, and the monolithic drivers will reduce the cost of TFT-LCDs. The conventional methods to fabricate poly-Si films are low pressure chemical vapor deposition (LPCVD0 as well as solid phase crystallization (SPC), pulsed rapid thermal annealing(PRTA), and eximer laser annealing (ELA). However, these methods have some disadvantages such as high deposition temperature over $600^{\circ}C$, small grain size (<50nm), poor crystallinity, and high grain boundary states. Therefore the low temperature and large area processes using a cheap glass substrate are impossible because of high temperature process. In this study, therefore, we have deposited poly-Si thin films on si(100) and glass substrates at growth temperature of below 40$0^{\circ}C$ using newly developed high rate magnetron sputtering method. To improve the sputtering yield and the growth rate, a high power (10~30 W/cm2) sputtering source with unbalanced magnetron and Si ion extraction grid was designed and constructed based on the results of computer simulation. The maximum deposition rate could be reached to be 0.35$\mu$m/min due to a high ion bombardment. This is 5 times higher than that of conventional sputtering method, and the sputtering yield was also increased up to 80%. The best film was obtained on Si(100) using Si ion extraction grid under 9.0$\times$10-3Torr of working pressure and 11 W/cm2 of the target power density. The electron mobility of the poly-si film grown on Si(100) at 40$0^{\circ}C$ with ion extraction grid shows 96 cm2/V sec. During sputtering, moreover, the characteristics of si source were also analyzed with in situ Langmuir probe method and optical emission spectroscopy.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.450-450
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• 2012

In recent days, advances in ZnO-based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). In particular, the development of high-mobility ZnO-based channel materials has been proven invaluable; thus, there have been many reports of high-performance TFTs with oxide semiconductor channels such as ZnO, InZnO (IZO), ZnSnO (ZTO), and InGaZnO (IGZO). The reliability of oxide TFTs can be improved by examining more stable oxide channel materials. In the present study, we investigated the effects of an ALD-deposited water vapor permeation barrier on the stability of ZnO and HfZnO (HZO) thin film transistors. The device without the water vapor barrier films showed a large turn-on voltage shift under negative bias temperature stress. On the other hand, the suitably protected device with the lowest water vapor transmission rate showed a dramatically improved device performance. As the value of the water vapor transmission rate of the barrier films was decreased, the turn-on voltage instability reduced. The results suggest that water vapor related traps are strongly related to the instability of ZnO and HfZnO TFTs and that a proper combination of water vapor permeation barriers plays an important role in suppressing the device instability.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.4
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• pp.650-656
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• 2018

The TFT-LCD industry is a kind of large-scale industrial Giant Microelectronics device industry and has a similar semiconductor process technology. Wet etching forms a relatively large proportion of the entire TFT process, but the number of published research papers on this topic is limited. The main reason for this is that the components of the etchant, in which the reaction takes place, are confidential and rarely publicized. Aluminum (Al) and copper (Cu), which have been used in recent years for the manufacture of large area LCDs, are very difficult materials to process using wet etching. Cu, a low-resistance material, can only be used in the wet etching process, and is used as a substitute for Al due to its high speed etching, low failure rate, and low power consumption. Further, the abnormal reaction of hydrogen peroxide ($H_2O_2$), which is used as an etching solution, requires additional piping and electrical safety devices. This paper proposes a method of minimizing the damage to the plant in the case of adverse reactions, though it cannot limit the adverse reaction of hydrogen peroxide. In recent years, there have been many cases in which aluminum etching equipment has been changed to copper. This paper presents a countermeasure against abnormal reactions by implementing safety PLC with a high safety grade.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1571-1578
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• 2013

With the emergence of high-integration array and large area panel process, the need to minimize the generation of particles in the field of semiconductor, LCD and OLED has grown. As an alternative to the conventional roller system, a contactless magnetic conveyor has been proposed to reduce the generation of particles. An EM-PM hybrid which is one of magnetic levitation types is already proposed for the conveyor system. One of problems pointed out with this approach is the vibration caused by the dynamic interaction between conveyor and rail. To reduce the vibration, the introduction of a secondary suspension system which aims to decouple the levitation electromagnet from the main body is proposed. The objective of this study is to develop a dynamic model for the magnetically levitated conveyor, and to investigate the effect of the introduced suspension system. An integrated model of levitation system and rail based on 3D multibody dynamic model is proposed. With the proposed model, the dynamic characteristics of maglev conveyor system are analyzed, and the effect of the secondary suspension and the stiffness and damping are investigated.