• 제목/요약/키워드: schottky effect

검색결과 147건 처리시간 0.064초

Effect of Recombination and Decreasing Low Current on Barrier Potential of Zinc Tin Oxide Thin-Film Transistors According to Annealing Condition

  • Oh, Teresa
    • Journal of information and communication convergence engineering
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    • 제17권2호
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    • pp.161-165
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    • 2019
  • In this study, zinc tin oxide (ZTO) thin-film transistors are researched to observe the correlation between the barrier potential and electrical properties. Although much research has been conducted on the electronic radiation from Schottky contacts in semiconductor devices, research on electronic radiation that occurs at voltages above the threshold voltage is lacking. Furthermore, the current phenomena occurring below the threshold voltage need to be studied. Bidirectional transistors exhibit current flows below the threshold voltage, and studying the characteristics of these currents can help understand the problems associated with leakage current. A factor that affects the stability of bidirectional transistors is the potential barrier to the Schottky contact. It has been confirmed that Schottky contacts increase the efficiency of the element in semiconductor devices, by cutting off the leakage current, and that the recombination at the PN junction is closely related to the Schottky contacts. The bidirectional characteristics of the transistors are controlled by the space-charge limiting currents generated by the barrier potentials of the SiOC insulated film. Space-charge limiting currents caused by the tunneling phenomenon or quantum effect are new conduction mechanisms in semiconductors, and are different from the leakage current.

Characterization of Conduction Mechanism in Cu Schottky Contacts to p-type Ge

  • Kim, Se Hyun;Jung, Chan Yeong;Kim, Hogyoung
    • Transactions on Electrical and Electronic Materials
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    • 제15권6호
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    • pp.324-327
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    • 2014
  • Germanium (Ge) is a promising material for next generation nanoelectronics and multiple junction solar cells. This work investigated the electrical properties in Cu/p-type Ge Schottky diodes, using current-voltage (I-V) measurements. The Schottky barrier heights were 0.66, 0.59, and 0.70 eV from the forward ln(I)-V, Cheung, and Norde methods, respectively. The ideality factors were 1.92 and 1.78 from the forward ln(I)-V method and Cheung method, respectively. Such high ideality factor could be associated with the presence of an interfacial layer and interface states at the Cu/p-Ge interface. The reverse-biased current transport was dominated by the Poole-Frenkel emission rather than the Schottky emission.

코발트 실리사이드 접합을 사용하는 0.15${\mu}{\textrm}{m}$ CMOS Technology에서 얕은 접합에서의 누설 전류 특성 분석과 실리사이드에 의해 발생된 Schottky Contact 면적의 유도 (Characterization of Reverse Leakage Current Mechanism of Shallow Junction and Extraction of Silicidation Induced Schottky Contact Area for 0.15 ${\mu}{\textrm}{m}$ CMOS Technology Utilizing Cobalt Silicide)

  • 강근구;장명준;이원창;이희덕
    • 대한전자공학회논문지SD
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    • 제39권10호
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    • pp.25-34
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    • 2002
  • 본 논문에서는 코발트 실리사이드가 형성된 얕은 p+-n과 n+-p 접합의 전류-전압 특성을 분석하여 silicidation에 의해 형성된 Schottky contact 면적을 구하였다. 역방향 바이어스 영역에서는 Poole-Frenkel barrier lowering 효과가 지배적으로 나타나서 Schottky contact 효과를 파악하기가 어려웠다. 그러나 Schottky contact의 형성은 순방향 바이어스 영역에서 n+-p 접합의 전류-전압 (I-V) 동작에 영향을 미치는 것으로 확인되었다. 실리사이드가 형성된 n+-p 다이오드의 누설전류 증가는 실리사이드가 형성될 때 p-substrate또는 depletion area로 코발트가 침투퇴어 Schottky contact을 형성하거나 trap들을 발생시켰기 때문이다. 분석결과 perimeter intensive diode인 경우에는 silicide가 junction area까지 침투하였으며, area intensive junction인 경우에는 silicide가 비록 공핍층이나 p-substrate까지 침투하지는 않았더라도 공핍층 근처까지 침투하여 trap들을 발생시켜 누설전류를 증가시킴을 확인하였다. 반면 p+-n 다이오드의 경우 Schottky contact이발생하지 않았고 따라서 누설전류도 증가하지 않았다. n+-p 다이오드에서 실리사이드에 의해 형성된 Schottky contact 면적은 순방향 바이어스와 역방향 바이어스의 전류 전압특성을 동시에 제시하여 유도할 수 있었고 전체 접합면적의 0.01%보다 작게 분석되었다.

Normally-Off Operation of AlGaN/GaN Heterojunction Field-Effect Transistor with Clamping Diode

  • Han, Sang-Woo;Park, Sung-Hoon;Kim, Hyun-Seop;Lim, Jongtae;Cho, Chun-Hyung;Cha, Ho-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권2호
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    • pp.221-225
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    • 2016
  • This paper reports a new method to enable the normally-off operation of AlGaN/GaN heterojunction field-effect transistors (HFETs). A capacitor was connected to the gate input node of a normally-on AlGaN/GaN HFET with a Schottky gate where the Schottky gate acted as a clamping diode. The combination of the capacitor and Schottky gate functioned as a clamp circuit to downshift the input signal to enable the normally-off operation. The normally-off operation with a virtual threshold voltage of 5.3 V was successfully demonstrated with excellent dynamic switching characteristics.

쇼트키 장벽 트랜지스터의 빛 조사에 따른 전기적 특성 연구 (Electric characteristics of Schottky barrier Field Effect Transistors with Halogen and Deuterium lamp)

  • 황민영;구상모
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2010년도 하계학술대회 논문집
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    • pp.348-348
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    • 2010
  • Nanostructures have great potential in various devices due to the their promising electronic and optical properties. Nano-patterned the front surface of a solar cell generally results in improved performance, mostly due to an increase in the short-circuit current by the incident photons strike the cell surface at an angle. In this work, we investigate AFM-assisted nano-patterned field effect transistors (FETs) with vairous silicon oxide distance value D, from ${\sim}0.5{\mu}m$ to $1{\mu}m$. Also, we compared the electro-optical characteristics of the patterned FETs and the non-patterned FETs (reference device) based on both 2-dimensional simulation and experimental results for the wavelength from 100nm to 900nm. In addition, we report electric characteristics for illuminated surface in schottky barrier field effect transistors (SB-FETs).

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A Semi-analytical Model for Depletion-mode N-type Nanowire Field-effect Transistor (NWFET) with Top-gate Structure

  • Yu, Yun-Seop
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제10권2호
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    • pp.152-159
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    • 2010
  • We propose a semi-analytical current conduction model for depletion-mode n-type nanowire field-effect transistors (NWFETs) with top-gate structure. The NWFET model is based on an equivalent circuit consisting of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic top-gate NWFET. The intrinsic top-gate NWFET model is derived from the current conduction mechanisms due to bulk charges through the center neutral region as well as of accumulation charges through the surface accumulation region, based on the electrostatic method, and thus it includes all current conduction mechanisms of the NWFET operating at various top-gate bias conditions. Our previously developed Schottky diode model is used for the MS contacts. The newly developed model is integrated into ADS, in which the intrinsic part of the NWFET is developed by utilizing the Symbolically Defined Device (SDD) for an equation-based nonlinear model. The results simulated from the newly developed NWFET model reproduce considerably well the reported experimental results.

High-Performance Schottky Junction for Self-Powered, Ultrafast, Broadband Alternating Current Photodetector

  • Lim, Jaeseong;Kumar, Mohit;Seo, Hyungtak
    • 한국재료학회지
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    • 제32권8호
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    • pp.333-338
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    • 2022
  • In this work, we developed silver nanowires and a silicon based Schottky junction and demonstrated ultrafast broadband photosensing behavior. The current device had a response speed that was ultrafast, with a rising time of 36 ㎲ and a falling time of 382 ㎲, and it had a high level of repeatability across a broad spectrum of wavelengths (λ = 365 to 940 nm). Furthermore, it exhibited excellent responsivity of 60 mA/W and a significant detectivity of 3.5 × 1012 Jones at a λ = 940 nm with an intensity of 0.2 mW cm-2 under zero bias operating voltage, which reflects a boost of 50 %, by using the AC PV effect. This excellent broadband performance was caused by the photon-induced alternative photocurrent effect, which changed the way the optoelectronics work. This innovative approach will open a second door to the potential design of a broadband ultrafast device for use in cutting-edge optoelectronics.

Low-Temperature Poly-Si TFT Charge Trap Flash Memory with Sputtered ONO and Schottky Junctions

  • An, Ho-Myoung;Kim, Jooyeon
    • Transactions on Electrical and Electronic Materials
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    • 제16권4호
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    • pp.187-189
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    • 2015
  • A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×105 and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm2/V·s at a drain voltage of −1 V, respectively.