• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4B
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• pp.695-703
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• 2010

In this paper, we propose an adaptive scalable encryption scheme for the layered architecture of SVC video. The proposed method determines an appropriate set of encryption algorithms to be applied for the layers of SVC by considering the importance and priority relationship among the SVC video layers. Unlike the conventional encryption method based on a fixed encryption algorithm for the whole video layers, the proposed method applies differentiated encryption algorithms with different encryption strength the importance of the video layers. Thereupon, higher security could be maintained for the lower video layer including more important data, while lower encryption strength could be applied for the higher video layer with relatively less important data. The effectiveness of the proposed adaptive scalable encryption method is proved by extensive simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.477-483
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• 2015

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.55-60
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• 2007

This paper proposes a fast and scalable priority queue architecture for use in high-speed networks which supports quality of service (QoS) guarantees. This architecture is cost-effective since a single queue can generate outputs to multiple out-links. Also, compared with the previous multiple systolic array priority queues, the proposed queue provides fast output generation which is important to high-speed packet schedulers, using a special control block. In addition this architecture provides the feature of high scalability.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.8
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• pp.1095-1102
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• 2021

A scalable ECC architecture with high scalability and flexibility between performance and hardware complexity is proposed. For architectural scalability, a modular arithmetic unit based on a one-dimensional array of processing element (PE) that performs finite field operations on 32-bit words in parallel was implemented, and the number of PEs used can be determined in the range of 1 to 8 for circuit synthesis. A scalable algorithms for word-based Montgomery multiplication and Montgomery inversion were adopted. As a result of implementing scalable ECC processor (sECCP) using 180-nm CMOS technology, it was implemented with 100 kGEs and 8.8 kbits of RAM when N_PE=1, and with 203 kGEs and 12.8 kbits of RAM when N_PE=8. The performance of sECCP with N_PE=1 and N_PE=8 was analyzed to be 110 PSMs/sec and 610 PSMs/sec, respectively, on P256R elliptic curve when operating at 100 MHz clock.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.353-357
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• 2014

This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.

• Journal of IKEEE
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• v.24 no.3
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• pp.901-908
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• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.802-805
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• 2007

A hardware architecture is presented of a wavelet based multiple line addressing driving scheme for passive matrix displays using the FPGA (Field Programmable Gate Arrays), which will be integrated in the scalable video coding $architecture^{[1]}$. The incoming compressed video data stream will then directly be transformed to the required column voltages by the hardware architecture without the need of employing the video decompression.

• Journal of KIISE:Information Networking
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• v.28 no.4
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• pp.578-585
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• 2001

IP Multicast that provides best-efforts service does not guarantee reliable delivery of multicast packets. In recent years, there are many approaches to support reliable multicast, but those are insufficient for implementing scalable and reliable multicast over Internet. We propose a Reliable Multicast Architecture(RMA) for scalable and reliable multicast. The RMA model guarantees reliability using a receiver initiated retransmission mechanism, and scalability using a feedback suppression mechanism by Multicast Router(MR). Furthermore, it utilizes underlying multicast routing information to minimize the cost of protocol modification and overheads. Our performance analyses show that RMA is much superior to previous works in the point of scalability and compatibility.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.937-940
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• 1993

A new hardware architecture achieves high speed, high precision fuzzy inference capabilities while maintaining Flexibility on par with software approaches. This flexibility allows unmodified, uncompromised porting of fuzzy system designs into hardware. The architecture is also scalable and offers data resolutions from 8 bits to 32 bits.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.113-113
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• 2004