Browse > Article

A Fast and Scalable Priority Queue Hardware Architecture for Packet Schedulers  

Kim, Sang-Gyun (School of Electrical Engineering & Computer Science, Kyungpook National University)
Moon, Byung-In (School of Electrical Engineering & Computer Science, Kyungpook National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.10, 2007 , pp. 55-60 More about this Journal
Abstract
This paper proposes a fast and scalable priority queue architecture for use in high-speed networks which supports quality of service (QoS) guarantees. This architecture is cost-effective since a single queue can generate outputs to multiple out-links. Also, compared with the previous multiple systolic array priority queues, the proposed queue provides fast output generation which is important to high-speed packet schedulers, using a special control block. In addition this architecture provides the feature of high scalability.
Keywords
Quality of Service;Priority Queue;Packet Scheduler;
Citations & Related Records
연도 인용수 순위
  • Reference
1 S. Moon, J. Rexford, and K. Shin, 'Scalable Haradware Priority Queue Architectures for High-Speed Packet Switches,' IEEE Trans. Comp, vol. 49, no. 11, pp. 1215-1226. Nov. 2000   DOI   ScienceOn
2 C.E. Leiserson, 'Systolic Priority Queues,' Proc. Caltech Conf. VLSI, pp. 200-214, Jan. 1979
3 J. Chao, 'A Novel Architecture for Queue Management in the ATM network,' IEEE J. Selected Areas in Comm. vol. 9, no. 7, pp. 1,110-1,118, Sept. 1991
4 P. Lavoie and Y. Savaria, 'A Systolic Architecture for Fast Stack Sequential Decoders,' IEEE Trans. Comm, vol. 42, nos. 2/3/4, pp. 324-334, Feb./Mar/Apr. 1994   DOI   ScienceOn
5 D. Picker and R. Fellman, 'A VLSI Priority Packet Queue with Inheritance and Overwrite,' IEEE Trans. Very Large Scale Integration Systems, vol. 3 no. 2, pp. 245-252, June. 1995   DOI   ScienceOn