• 한국컴퓨터정보학회논문지
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• 제25권2호
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• pp.21-29
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• 2020

IT 산업 환경에서 모바일 데이터의 수요 증가로 인해 NAND 플래시 메모리의 사용이 지속적으로 증가하고 있다. 하지만, 플래시 메모리의 소거 동작은 긴 대기 시간과 높은 소비 전력을 요구하여 각 셀의 수명을 제한한다. 따라서 쓰기와 삭제 작업을 자주 수행하면 플래시 메모리의 성능과 수명이 단축된다. 이런 문제를 해결하기 위해 디스크 버퍼를 이용, 플래시 메모리에 할당되는 쓰기 및 지우기 연산을 감소시켜 플래시 메모리의 성능을 향상시키는 기술이 연구되고 있다. 본 논문에서는 쓰기 횟수를 최소화하기 위한 CPWL 기법을 제안한다. CPWL 기법은 버퍼 메모리 액세스 패턴에 따라 읽기 및 쓰기 페이지를 나누어 관리한다. 이렇게 나뉜 페이지를 정렬하여 쓰기 횟수를 줄이고 결과적으로 플래시 메모리의 수명을 늘리고 에너지 소비를 감소시킨다.

• 정보처리학회논문지A
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• 제11A권3호
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• pp.157-162
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• 2004

본 논문에서는 가상 메모리 압축 알고리즘으로 CAMD 알고리즘을 제안한다. CAMD 알고리즘은 페이지 폴트가 일어났을 때 이들 페이지들을 스왑 디바이스로 이동시키지 않고 주기억장치 내의 압축된 캐시 영역을 할당하여 압축된 페이지를 저장한다. 이렇게 함으로써 스왑 디바이스로 이동하는 시간과 횟수를 감소시켜서 페이지 폴트 응답시간을 줄이며 주기억장치에 저장되는 페이지들의 공간 활용도를 높일 수 있다. 메모리 내의 데이터는 일반적인 압축 알고리즘에서 다루는 데이터와는 다른 특징들을 가지고 있어서 메모리 내의 주소 값이나 배열 데이터와 값은 요소들을 고려하여 압축될 때의 효율성을 높일 수 있다.

• 대한임베디드공학회논문지
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• 제11권2호
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• pp.117-123
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• 2016

In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

• ETRI Journal
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• 제37권4호
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• 대한임베디드공학회논문지
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• 제14권2호
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• pp.87-96
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• 2019

Low power issue is one of the most critical problems in the Internet of Things (IoT), which are powered by battery. To solve this problem, various approaches have been presented so far. In this paper, we propose a method to reduce the power consumption by reducing the numbers of accesses into the flash memory consuming a large amount of power for on-chip software execution. Our approach is based on using cooperative logging structure to distribute the sampling overhead in single sensor node to adjacent nodes in case of rare-event applications. The proposed algorithm to identify event occurrence is newly introduced with negative feedback method by observing difference between past data and recent data coming from the sensor. When an event with need of flash access is determined, the proposed approach only allows access to write the sampled data in flash memory. The proposed event detection algorithm (EDA) result in 30% reduction of power consumption compared to the conventional flash write scheme for all cases of event. The sampled data from the sensor is first traced into the random access memory (RAM), and write access to the flash memory is delayed until the page buffer of the on-chip flash memory controller in the micro controller unit (MCU) is full of the numbers of the traced data, thereby reducing the frequency of accessing flash memory. This technique additionally reduces power consumption by 40% compared to flash-write all data. By sharing the sampling information via LoRa channel, the overhead in sampling data is distributed, to reduce the sampling load on each node, so that the 66% reduction of total power consumption is achieved in several IoT edge nodes by removing the sampling operation of duplicated data.

• ETRI Journal
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• 제26권6호
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• pp.615-621
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• 2004

Next generation mobile communication system, such as IMT-2000, adopts Turbo codes due to their powerful error correction capability. This paper presents a block-wise maximum a posteriori (MAP) Turbo decoding structure with a low memory requirement. During this research, it has been observed that the training size and block size determine the amount of required memory and bit-error rate (BER) performance of the block-wise MAP decoder, and that comparable BER performance can be obtained with much shorter blocks when the training size is sufficient. Based on this observation, a new decoding structure is proposed and presented in this paper. The proposed block-wise decoder employs a decoding scheme for reducing the memory requirement by setting the training size to be N times the block size. The memory requirement for storing the branch and state metrics can be reduced 30% to 45%, and synthesis results show that the overall memory area can be reduced by 5.27% to 7.29%, when compared to previous MAP decoders. The decoder throughput can be maintained in the proposed scheme without degrading the BER performance.

• 한국컴퓨터정보학회논문지
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• 제24권3호
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• pp.1-9
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• 2019

This paper presents three potential risks in an environment that simultaneously performs the garbage collection and wear leveling in NAND flash memory. These risks may not only disturb the lifespan improvement of NAND flash memory, but also impose an additional overhead of page migrations. In this paper, we analyze the interference of garbage collection and wear leveling and we also provide two theoretical considerations for lifespan prolongation of NAND flash memory. To prove two solutions of three risks, we construct a simulation, based on DiskSim 4.0 and confirm realistic impacts of three risks in NAND flash memory. In experimental results, we found negative impacts of three risks and confirmed the necessity for a coordinator module between garbage collection and wear leveling for reducing the overhead and prolonging the lifespan of NAND flash memory.

• 한국전자거래학회지
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• 제14권4호
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• pp.119-131
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• 2009

최근 전자상거래 환경에서 실시간 트랜잭션 처리가 필요한 환경들이 많아지고 있다. 이동 통신, 금융시장 환경에서 빠른 실시간 트랜잭션 처리 지원을 위한 메인메모리 데이터베이스에 대한 연구와 구축이 많아졌다. 빠른 트랜잭션 지원을 위한 인덱싱 기법에 대한 연구로는 최근 마이크로 프로세서의 구조와 기능을 이용하여 캐시미스 수를 줄이거나 캐시 미스 발생시에 데이터 접근 지연시간을 줄이기 위한 방법들에 대한 연구가 수행되고 있다. 본 논문은 최근 마이크로 프로세서에서 지원하고 있는 프리패치 기법을 이용하여 캐시 미스 시에 데이터 접근 지연시간을 줄이는 트리인덱스 프리패치 기법을 제안한다. 또한 프리패치 기법에 효과적인 pCST-트리 인덱스 구조를 제안하고 실험을 통해 제안한 트리의 우수성을 제시한다.

• 한국자동차공학회논문집
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• 제17권3호
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• pp.127-141
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• 2009

While the ever-increasing complexity of automotive software systems can be effectively managed through the adoption of a reliable real-time operating system (RTOS), it may incur additional resource usage to a resultant system. Due to the mass production nature of the automotive industry, reducing physical resources used by automotive software is of the utmost importance for cost reduction. OSEK OS is an automotive real-time kernel standard specifically defined to address this issue. Thus, it is very important to develop and exploit kernel mechanisms such that they can achieve minimal resource usage in the OSEK OS implementation. In this paper, we analyze the task subsystem, resource subsystem, application mode and conformance classes of OSEK OS as well as the OSEK Implementation Language (OIL). Based on our analysis, we in turn devise and implement kernel mechanisms to minimize the dynamic memory usage of the OSEK OS implementation. Finally, we show that our mechanisms effectively reduce the memory usage of OSEK OS and applications.

• ETRI Journal
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• 제35권1호
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• pp.154-157
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• 2013

This letter proposes a memory-based parallel string matching engine using the compressed state transitions. In the finite-state machines of each string matcher, the pointers for representing the existence of state transitions are compressed. In addition, the bit fields for storing state transitions can be shared. Therefore, the total memory requirement can be minimized by reducing the memory size for storing state transitions.