1 |
R. F Freitas, W.W. Wilcke, "Storage- Class Memory: the Next Storage System Technology," IBM Journal of Research and Development, Vol. 52, No. 4.5, pp. 439-447, 2008.
DOI
|
2 |
G. Dhiman, R Ayoub, T. Rosing, "PDRAM: A Hybrid PRAM and DRAM Main Memory System," Proceedings of Design Automation Conference, pp. 664-669, 2009.
|
3 |
B.S. Jung, J.H. Lee, "Analysis on the Effectiveness of the Filter Buffer for Low Power NAND Flash Memory," IEMEK J. Embed. Sys. Appl., Vol. 7, No. 4, pp. 201-207, 2012 (in Korea).
DOI
|
4 |
H. Seok, Y. Pack, K.W. Park, K.H. Pack, " Efficient Page Caching Algorithm with Prediction and Migration for a Hybrid Main Memory," ACM, SIGAPP Applied Computing Review, Vol. 11, No. 4, pp. 38-48, 2011.
|
5 |
M.K. Qureshi, V. Srinivasan, J.A. Rivers, "Scalable high performance main memory system using phase-change memory technology," Proceedings of the 36th annual international symposium on Computer architecture, pp. 24-33, 2009.
|
6 |
S. Lee, H. Bahn, S.H. Noh, "CLOCK- DWF:A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architecture," IEEE Transactions on Computers, Vol. 63. No. 9, pp.2187-2200, 2013.
DOI
|
7 |
N. Nethercote, J. Seward, "Valgrind: A Program Supervision Framwork," Elsevier Electonc Notes in Theoretical Computer Science, Vol. 89, No. 2, pp. 44-66, 2003.
DOI
|
8 |
S,Eilet, M. Leinwander, G. Crisenza, "Phase Change Memory: A new memory technology to enable new memory usage models," Proceedings of IEEE International Memory Workshop, pp. 1-2, 2009.
|