• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.10
• /
• pp.46-53
• /
• 2011

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. The CCI is a critical factor which affects occurring data errors in a cell, when surrounding cells are programed. We derived a characteristic equation for CCI considering write procedure of data that is similar with signal equalizing. The model considers the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. We verify the proposed equalizer comparing with the measured data of 1-block MLC NAND flash memory. As the simulation result, the equalizer shows an error correction ratio about 60% under 20nm NAND process.

• Journal of KIISE:Computer Systems and Theory
• /
• v.27 no.4
• /
• pp.383-393
• /
• 2000

In shared memory multiprocessor systems, false sharing occurs when several independent data objects, not shared but accessed by different processors, are allocated to the same coherency unit of memory. False sharing is one of the major factors that may degrade the performance of memory coherency protocols. This paper presents a new shared memory allocation scheme to reduce false sharing of parallel applications where master processor controls allocation of all the shared objects. Our scheme allocates the objects to temporary address space for the moment, and actually places each object in the address space of processor that first accesses the object later. Its goal is to allocate independent objects that may have different access patterns to different pages. We use execution-driven simulation of real parallel applications to evaluate the effectiveness of our scheme. Experimental results show that by using our scheme a considerable amount of false sharing faults can be reduced with low overhead.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.4
• /
• pp.1098-1105
• /
• 1999

The caches in distributed shared memory systems enhance the performance by reducing memory access latency and communication overhead, but they must solve the cache coherence problem. This paper proposes a new directory protocol to solve the cache coherence problem and to improve the system performance in distributed shared memory systems. To maintain the cache coherence of shared data, processors within a limited distance reduce the communication overhead by using a bit-vector like the full directory scheme. Processors over a limited distance store pointers in a directory pool. Since the bit-vector and the directory pool remove the unnecessary cache invalidations, the proposed scheme reduces the communication traffic and improves the system performance. The dynamic limited directory scheme reduces the communication traffic up to 66 percents compared with the limited directory scheme and the number of directory access up to 27 percents compared with the dynamic pointer allocation scheme.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.7
• /
• pp.1371-1378
• /
• 2009

We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.24 no.1
• /
• pp.97-101
• /
• 2024

In this paper, we present the implementation of proton beam irradiation test logic and test results for Xilinx's RFSoC FPGA. In addition to the FPGA function, RFSoC is a chip that integrates CPU, ADC, and DAC and is attracting attention in the defense and space industries aimed at reducing the size of the chip. In order to use these chips in a space environment, an analysis of radiation effects was required and radiation mitigation measures were required. Through the proton irradiation test, the logic to measure the radiation effect of RFSoC was designed. Logic for comparing values stored in memory with normal values was implemented, and protons were irradiated to RFSoC to measure SEU generated in the block memory area. To alleviate the occurrence of SEU in other areas, TMR and SEM were applied and designed. Through the test results, we intend to verify this test configuration and establish an environment in which logic design for satellites can be verified in the future.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.485-488
• /
• 2004

As scaling down the cell channel length, the increment of B concentration in channel region is inevitable to overcome the punch-through, especially in flash memory cell with 90nm technology. This paper shows that the high dose ion implantation in channel cause the Si defect. which has been proved to be the major cause of the tailed Vth in distribution. And also mechanical stress due to SiN-anneal process can induce the Si dislocation. and get worse it. With decreasing the channel implantation dose, skipping the anneal and reducing the mechanical stress, Si defect problem is solved completely. We are verify first that the optimization of B concentration in channel must be certainly considered in order to improve Si defect. It is also certainly necessary to stabilize the distribution of cell Vth in the next generation of flash memory.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.11
• /
• pp.11-18
• /
• 2007

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems such as WiBro, DAB and UWB systems. Most of the researches on the implementation of FFT processors have focused on reducing the complexities of multipliers, memory and control circuits. In this paper, to reduce the memory size required for IFFT(Inverse Fast Fourier Transform), we propose a new IFFT design method based on a mapping method. By simulations, it is shown that the reposed IFFT design method achieves more than 60% area reduction and much SQNR(Signal-to-Quantization-Noise Ratio) gain compared with previous IFFT circuits.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.3
• /
• pp.331-340
• /
• 2012

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction-double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in reduced area overhead. A detailed implementation using fuse technology is also proposed in this paper.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.13 no.5
• /
• pp.269-277
• /
• 2018

NAND flash memory has widely been used because of non-volatility, low power consumption and fast access time. However, it suffers from inability to provide update-in-place and the erase cycle is limited. The unit of read/write operation is a page and the unit of erase operation is a block. Moreover erase operation is slower than other operations. We proposed the Adaptive Garbage Collection (called "AGC") policy which focuses on not only reducing garbage collection process time for real-time guarantee but also wear-leveling for a flash memory lifetime. The AGC performs better than Cost-benefit policy and Greedy policy. But the AGC does not consider the operation characteristics. So we proposed the Advanced Adaptive Garbage Collection (called "A-AGC") policy which considers the page write operation count and block erase operation count. The A-AGC reduces the write operations by considering the data update frequency and update data size. Also, it reduces the erase operations by considering the file fragmentation. We implemented the A-AGC policy and measured the performance compared with the AGC policy. Simulation results show that the A-AGC policy performs better than AGC, specially for append operation.

• Proceedings of the Optical Society of Korea Conference
• /
• 2000.02a
• /
• pp.168-169
• /
• 2000

We have tried to enhance the density of the near-field optical memory and to improve the recording/readout speed. The current optical memory has the limitation in both density and speed. This barrier due to the far-field nature can be overcome by the use of the near-field$^{(1)}$ . The optical data storage density can be increased by reducing the size of the nanometric aperture where the near-field is obtained. To fabricate the aperture in precise dimension, we applied the orientation-dependent / anisotropic etching property of crystal Si often employed in the field of MEMS$^{(2)}$ . And so we fabricated the 10$\times$10 aperture array. This array will be also the indispensable part for speeding up. One will see the possibility of the multi-tracking pickup in the phase changing type memory through this array$^{(3)}$ . This aperture array will be expected to write the bit-mark whose size is about 100nm. We will show the recent result obtained. (omitted)