• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.274-277
• /
• 2000

Thin Film Transistor(TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature(500$^{\circ}C$) Metal-Induced Lateral Crystallization(MILC) furnace annealing and high -temperature (700$^{\circ}C$) rapid thermal annealing leads to the improvement of the material quality The TFTs measured with this two-step annealing material exhibit better characteristics than those obtained by using conventional MILC furnace annealing.

• Korean Journal of Materials Research
• /
• v.27 no.2
• /
• pp.94-99
• /
• 2017

Dinickel-silicide $(Ni_2Si)/glass$ was employed as a counter electrode for a dye-sensitized solar cell (DSSC) device. $Ni_2Si$ was formed by rapid thermal annealing (RTA) at $700^{\circ}C$ for 15 seconds of a 50 nm-Ni/50 nm-Si/glass structure. For comparison, $Ni_2Si$ on quartz was also prepared through conventional electric furnace annealing (CEA) at $800^{\circ}C$ for 30 minutes. XRD, XPS, and EDS line scanning of TEM were used to confirm the formation of $Ni_2Si$. TEM and CV were employed to confirm the microstructure and catalytic activity. Photovoltaic properties were examined using a solar simulator and potentiostat. XRD, XPS, and EDS line scanning results showed that both CEA and RTA successfully led to tne formation of nano $thick-Ni_2Si$ phase. The catalytic activity of $CEA-Ni_2Si$ and $RTA-Ni_2Si$ with respect to Pt were 68 % and 56 %. Energy conversion efficiencies (ECEs) of DSSCs with $CEA-Ni_2Si$ and $RTA-Ni_2Si$catalysts were 3.66 % and 3.16 %, respectively. Our results imply that nano-thick $Ni_2Si$ may be used to replace Pt as a reduction catalytic layer for a DSSCs. Moreover, we show that nano-thick $Ni_2Si$ can be made available on a low-cost glass substrate via the RTA process.

• Korean Journal of Metals and Materials
• /
• v.50 no.8
• /
• pp.557-562
• /
• 2012

Self-organized ruthenium (Ru) dots were fabricated by $400^{\circ}C$ RTA (rapid thermal annealing) and ALD (atomic layer deposition). The dots were produced under the $400^{\circ}C$ RTA conditions for 10, 30 and 60 seconds on all Si(100)/200 nm-SiO2, glass, and glass/fluorine-doped tin oxide (FTO) substrates. Electrical sheet resistance, and surface microstructure were examined using a 4-point probe and FE-SEM (field emission scanning electron microscopy). Ru dots were observed when a 30 nm-Ru layer on a Si(100)/200 nm-SiO2 substrate was annealed for 10, 30 and 60 seconds, whereas the dots were only observed on a glass substrate when a 50 nm-Ru layer was annealed on glass. For a glass/FTO substrate, RTA <30 seconds was needed for 30 nm Ru thick films. Those dots can increase the effective surface area for silicon and glass substrates by up to 5-44%, and by 300% for the FTO substrate with a < $20^{\circ}$ wetting angle.

• Journal of the Korean institute of surface engineering
• /
• v.52 no.3
• /
• pp.123-129
• /
• 2019

With recent demand for the renewable energy resources, we conducted a research on the energy conversion and storage device of supercapacitor. The hybrid graphene-zinc oxide(GZO) electrodes for the supercapacitors (SCs) were fabricated and investigated. To increase the electrical conductivity of the GZO electrode, the rapid thermal annealing(RTA) in $Ar/H_2$(10%) atmosphere was applied and the effect was examined by comparing it with RTA at Ar atmosphere. In Raman spectroscopy, the electrodes annealed at 400? in $Ar/H_2$ atmosphere showed a lower ratio of D/G peak than that of annealed at Ar atmosphere, and had a larger specific capacitance(Sc) in the cyclic voltammetry(CV), and a lower the equivalent series resistance(ESR) in the electrochemical impedance spectroscopy(EIS). The reason seems to come from the better mixing of the graphene and zinc oxide by the RTA in $Ar/H_2$(10%).

• Journal of the Semiconductor & Display Technology
• /
• v.23 no.1
• /
• pp.88-91
• /
• 2024

The europium doped yttrium oxide (Y₂O₃:Eu³⁺) thin film was formed on a Si substrate by the conventional spin-coating process followed by rapid thermal annealing (RTA) treatment. The spinning profiles such as rotation speed, acceleration and holding times were controlled during the spin-coating process for the best condition of the Y₂O₃:Eu³⁺ thin film. The RTA treatment was conducted for several temperature in order to crystallize the spin coated film. The Y₂O₃:Eu³⁺ thin film presented best performance in the conditions of 4000 rpm, 30 s and 10 s of rotation speed, acceleration time and holding time, respectively, at a fixed RTA temperature of 900 ℃.

• Journal of the Semiconductor & Display Technology
• /
• v.21 no.3
• /
• pp.105-109
• /
• 2022

For the realization of higher reliable transition metal dichalcogenide layer, molybdenum disulfide was formed on sapphire substrate by direct current sputtering and subsequent rapid thermal annealing process. Unlike RF sputtered MoS₂ thin films, DC sputtered showed no irregular holes and protrusions after annealing process from scanning electron microscope images. From atomic force microscope results, it was possible to investigate that surface roughness of MoS₂ thin films were more dependent on DC sputtering power then annealing temperature. On the other hand, the Raman scattering spectra showed the dependency of significant E¹_2g and A¹_g peaks on annealing temperatures.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.29 no.2
• /
• pp.50-53
• /
• 2019

In this study, polycrystalline silicon thin film useful for the solar cells was fabricated by AIC(Aluminum Induced Crystallization) process. A diffusing barrier for this process is prepared with $Al_2O_3$. For the maximization of the grain size of the polycrystalline silicon, a selective blasting of the $Al_2O_3$ diffusing barrier was conducted before annealing treatment. The heat treatment for the activation of the amorphous-Si (a-Si) layer was carried out with Rapid Thermal Annealing (RTA) process. Crystallization of the a-Si layer was analyzed with XRD. It was confirmed that a-Si was crystallized at $500^{\circ}C$ and the silicon crystal is observed to be formed and the grain size of the polycrystalline silicon was observed to be $15.9{\mu}m$.

• Journal of the Optical Society of Korea
• /
• v.20 no.1
• /
• pp.130-134
• /
• 2016

The influence of Au/Ni-based contact formed on a lightly-doped (7.3×1017cm−3, Zn-doped) InGaAsP layer for electrical compensation of surface plasmon polariton (SPP) propagation under various rapid thermal annealing (RTA) conditions has been studied. The active control of SPP propagation is realized by electrically pumping the InGaAsP multiple quantum wells (MQWs) beneath the metal planar waveguide. The metal planar film acts as the electric contact layer and SPP waveguide, simultaneously. The RTA process can lower the metal-semiconductor electric contact resistance. Nevertheless, it inevitably increases the contact interface morphological roughness, which is detrimental to SPP propagation. Based on this dilemma, in this work we focus on studying the influence of RTA conditions on electrical control of SPPs. The experimental results indicate that there is obvious degradation of electrical pumping compensation for SPP propagation loss in the devices annealed at 400℃ compared to those with no annealing treatment. With increasing annealing duration time, more significant degradation of the active performance is observed even under sufficient current injection. When the annealing temperature is set at 400℃ and the duration time approaches 60s, the SPP propagation is nearly no longer supported as the waveguide surface morphology is severely changed. It seems that eutectic mixture stemming from the RTA process significantly increases the metal film roughness and interferes with the SPP signal propagation.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.164-164
• /
• 2010

Cds films were deposited on glass substrates using rf magnetron sputtering method followed by rapid thermal annealing(RTA). Effects of annealing temperature on surface characteristic, structural, electrical and optical property of CdS films were investigated at different temperatures ranging from 250 to $550^{\circ}C$ with various holding time. The film annealed at $450^{\circ}C$ with less than 1 min holding time is attributed to the improved crystalline quality of CdS film due to the effective relaxation of residual compressive stress and achieving maximum grain size. The results show that RTA treatments under optimal annealing condition can provide significant improvements in the properties of CdS films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.11a
• /
• pp.136-139
• /
• 1999

The post-annealing treatments on RF (Radio Frequency) magnetron sputtered PZI(Pb$\_$1.05/(Zr$\_$0.52/, Ti$\_$0.48/)O$_3$thin films(4000${\AA}$) have been investigated. for a structure of PZT/Pt/Ti/SiO$_2$/Si Crystallization pproperties of PZT films were strongly dependent on RTA(Rapid Thermal Annealing) annealing temperature. We were able to obtain a perovskite structure of PZT at a low temperature of 600$^{\circ}C$. P-E curves of Pd/PZT/Pt capacitor annealed at 700$^{\circ}C$ demonstrate typical hysteresis loops. The measured values of P$\_$r/, E$\_$c/, by post annealed at 700$^{\circ}C$ were 12.1 ${\mu}$C/$\textrm{cm}^2$, 120KV/cm respectively.