• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.7
• /
• pp.1455-1462
• /
• 2012

In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $289.9{\mu}m{\times}163.65{\mu}m$ ($=0.0475mm^2$).

• 한국전산유체공학회:학술대회논문집
• /
• 2005.04a
• /
• pp.100-103
• /
• 2005

This work discusses the numerical analysis, the design and experimental test of the SMA (Shape Memory Alloy) actuator along with its capabilities and limitations. Convection heating and cooling using water actuate the SMA element of the actuator. The fuel such as propane, having a high energy density, is used as the energy source for the SMA actuator in order to increase power and energy density of the system, and thus in order to obviate the need for electrical power supplies such as batteries. The system is composed of a pump, valves, bellows, a heater (burner), control unit and a displacement amplification device. The actuation frequency is compared with the prediction obtained from numerical analysis. For the designed SMA actuator system, the results of numerical analysis were utilized in determining design parameters and operating conditions.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.10a
• /
• pp.548-551
• /
• 2003

JSize is a Java equivalent of the Unix size program. The Unix size program analyses an executable file and estimates the size of code and data segment when the file is loaded on memory. Likewise, JSize analyze a Java class file and estimates the size of class area when the file is loaded on memory. This paper presents the principles necessary to estimate the class area size with the information obtained from a class file. An experimental result is included to show the accuracy of estimation the JSize provides.

• The KIPS Transactions:PartD
• /
• v.15D no.1
• /
• pp.99-106
• /
• 2008

Recently developed compilers perform some optimizations in order to speed up the execution time of source program. These optimizations require the reordering of the sequence of program statements. This reordering does not give any problems in a single-threaded program. However, the reordering gives some significant errors in a multi-threaded program. State-of-the-art model checkers such as JavaPathfinder do not consider the reordering resulted in the optimization step in a compiler since they just consider a single memory model. In this paper, we develop a new verification tool to verify Java source program based on Java Memory Model. And our tool is capable of handling the reordering in verifying Java programs. As a result, our tool finds an error in the test program which is not revealed with the traditional model checker JavaPathFinder.

• KIPS Transactions on Computer and Communication Systems
• /
• v.5 no.1
• /
• pp.1-6
• /
• 2016

This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.

• International journal of advanced smart convergence
• /
• v.6 no.1
• /
• pp.26-31
• /
• 2017

When mobile navigator device accesses data randomly, the cache memory performance is rapidly deteriorated due to low memory access locality. For instance, GPS (General Positioning System) of navigator program for automobiles or drones, that are currently in common use, uses data from 32 satellites and computes current position of a receiver. This computation of positioning is the major part of GPS which accounts more than 50% computation in the program. In this computation task, the satellite signals are received in real time and stored in buffer memories. At this task, since necessary data cannot be sequentially stored, the data is read and used at random. This data accessing patterns are generated randomly, thus, memory system performance is worse by low data locality. As a result, it is difficult to process data in real time due to low data localization. Improving the low memory access locality inherited on the algorithms of conventional communication applications requires a certain optimization technique to solve this problem. In this study, we try to do optimizations with data and memory to improve the locality problem. In experiment, we show that our case study can improve processing speed of core computation and improve our overall system performance by 14%.

• International Journal of Internet, Broadcasting and Communication
• /
• v.14 no.3
• /
• pp.230-242
• /
• 2022

The purpose of this study was to verify the effectiveness of the computerized cognitive rehabilitation program in which areas and to suggest effective ways to utilize the program in the future, being conducted for 20 college students. We lasted this study from May 3 to 23, 2021. As a result of analyzing the groups using the Computer-based Cognitive Rehabilitation Program (CoTras), in terms of the difference in accuracy for the case of visual perception group B was statistically significantly improved than group C(p<0.05). In the case of attention, memory, and orientation, there was no significant difference between groups(p>0.05). In the case of reaction time difference, there was no significant difference between groups in visual perception, concentration, memory, and orientation(p>0.05). And in order to improve attention and visual perception, it is recommended to conduct the program three times with a duration of 20 minutes, and in order to improve orientation and memory, it can be said that it is helpful to conduct one experiment for at least 30 minutes rather than conducting short and frequent experiments. Through this study, we found that it is effective to apply different times according to each area to improve cognitive function. In other words, depending on the purpose of which cognitive function is to be improved, the duration of the program should be applied differently.

• Proceedings of the KIEE Conference
• /
• 1991.11a
• /
• pp.185-188
• /
• 1991

In this paper we have designed and implemented a method of using extended memory and hard disk space as a data buffer for application programs to allow handling of large data files in DOS environment. We use a part of the conventional DOS memory as a buffer cache which allows the application program to use extended memory and hard disks transparently. Using buffer cache also allows some speed improvement for the application program. We have also implemented a number of functions to allow easier handling of pointer operations used by application programs.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.245-248
• /
• 1998

Until now, to solve the problem, the lack of memory at TDX-10A ESS (Electronic Switching System), we have extended only main memory of the systems. However, this method is useful for only Transitcall Processing Subsystems and, it is not an effective way that is able to apply to all Subsystems of ESS because of the financial aspect. In this paper, we will introduce a new method which uses Non-Resident Program. This method utilizes main memory more effectively. We will also analyze the effectiveness resulting from test of new method applied to TDX-10A ESS.

• 전기의세계
• /
• v.23 no.1
• /
• pp.73-78
• /
• 1974

Digital simulation algorithms and program for multimachine dynamic stability have been developed which represent the effects of machines much more complety than have been available previously. Emphasis is given to the savings of the memory spaces required, thus making it possible to use a small computer with limited capacity of core storage (without auxiliary storage). Both d- and q- aris quantities are fully represented, and the speed-governing and voltage-regulating system available are ertensive, thus allowing a very close approximation to any physical system. Facilities for dynamic and nonlinear loads are also included. The computational algorithms and program developed have been shown to be extensive and complete, and are very desirable features minimizing memory spaces for stability calculations. The capabilities have been demonstrated by several case studies for an actual power system of 44 generators, 22 loads and 33 buses. About 13-K words of memory spaces have been required for the case studies on the basis of two words per real variable and a word per integer variable.