• Journal of IKEEE
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• v.22 no.3
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.23-30
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• 2012

This paper proposes a novel adaptive header-based power gating structure to compensate for the performance loss and the increased wake-up time of the power gating structures induced by the negative bias temperature instability (NBTI) effect. The proposed structure consists of variable width footers based on the two-pass power gating and a new NBTI sensing circuit for an adaptive control. The simulation results of the proposed structure are compared to those of power gating without the adaptive control and show that both the circuit-delay and wake-up time dependence of the power gating structure on the NBTI stress is minimized with only 3% and 4% increase, respectively while keeping small leakage power and rush-current. In this paper, a 45 nm CMOS technology and predictive NBTI model have been used to implement the proposed circuits.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.28-35
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• 2015

In this paper, we propose to identify redundant power states of high-level power model based on clock gating enable signals(CGENs) using dependencies of Boolean functions and structural dependencies of clock gating cells. Three functional dependencies between two CGENs, namely equvalence, inversion, and inclusion, are used. Functions of CGENs in a circuit are represented by binary decision diagrams (BDDs) and the functional relations are used to reduce the number of power states. The structural dependency appears when a clock gating cell drives another clock gating cells in a circuit. Automatic dependency checking algorithm has been proposed. The experimental results show the average number of power state is reduced by 59%.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.1
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• pp.88-99
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• 2007

In this paper, a novel new pulse power generator based on IGBT stacks is proposed for pulse power application. Because it can generate up to 60kV pulse output voltage without any step- up transformer or pulse forming network, it has advantages of fast rising time, easiness of pulse width variation and rectangular pulse shape. Proposed scheme consists of series connected 9 power stages to generate maximum 60kV output pulse and one series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 850VDC pulse. Finally pulse output voltage is applied using total 72 series connected IGBTs. To reduce component for gate power supply, a simple and robust gate drive circuit is proposed. For gating signal synchronization, full bridge invertor and pulse transformer generates on-off signals of IGBT gating with gate power simultaneously and it has very good characteristics of short circuit protection.

• Journal of IKEEE
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• v.22 no.3
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• pp.842-845
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• 2018

In this paper, we propose low-power operational methods for thermal-energy-harvesting sensor circuits. Here, the amount of harvested current has been measured as low as 8uA. However the DC power consumption of the sensor circuit is known to consume much larger than 8uA. Thus, We propose the hardware-based power gating and software-based active/sleep timing control schemes, respectively, for controlling the power consumption of sensor circuit. In the hardware-based power gating scheme, if the ratio of Toff/Ton is larger than 22, the sensor can consume less than 8uA. For the software-based active/sleep control scheme, if the ratio of Tslp/Tact is larger than 3, we can suppress the current consumption below 8uA. The hardware-based and software-based schemes proposed in this paper would be helpful in various applications of energy-harvesting sensor circuits, where the power consumption is limited by an amount of harvested energy.

• Proceedings of the KIPE Conference
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• 2007.11a
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• pp.43-46
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• 2007

In this paper, a novel new pulse power generator based on IGBT stacks is proposed for pulse power application. Proposed scheme consists of series connected 9 power stages to generate maximum 60kV output pulse and one series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 850VDC pulse. Finally pulse output voltage is applied using total 72 series connected IGBTs. The synchronization of gating signal is important for series operation of IGBTs. For gating signal synchronization, full bridge inverter and pulse transformer generates on-off signals of IGBT gating and specially designed gate power circuit was used. Proposed scheme has lots of advantages such as long lifecyle, compact size, flat topped pulse forming, small weight, protection for arc, high efficiency and flexibility to generate various kinds of pulse output.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.917-918
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• 2006

In this paper, a novel new pulse power generatorbased on IGBT stacks is proposed for pulse power application. Proposed scheme consists of series connected 9power stages to generate maximum 60kV output pulse and one series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 850VDC pulse. Finally pulse output voltage is applied using total 72 series connected IGBTs. The synchronization of gating signal is importantfor series operation of IGBTs. For gating signal synchronization, full bridge inverter and pulse transformer generates on-off signals of IGBT gating and specially designed gate power circuit was used.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.904-905
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• 2008

In this paper, a novel 60kV, 300A, 3kHz pulsed power supply based on IGBT stacks is proposed. Proposed scheme consists of series connected 9 power stages to generate maximum 60kV output pulse and 15kW series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 830VDC, 300A pulses. Finally pulse output voltage is applied using total 72 series connected IGBTs. The synchronization of gating signal is important of series operation of IGBTs. For gating signal synchronization, full bridge inverter and pulse transformer generates on-off signals of IGBT gating and specially designed gate power circuit was used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.555-562
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• 2008

In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.209-213
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• 2017

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.