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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Self-Power Gating Technique For Low Power Asynchronous Circuit

  • Mai, Kim-Ngan Thi (Faculty of Electrical and Electronics Engineering, Ho Chi Minh Univeristy of Technology and Education) ;
  • Vo, Huan Minh (Faculty of Electrical and Electronics Engineering, Ho Chi Minh Univeristy of Technology and Education)
  • Received : 2018.08.08
  • Accepted : 2018.09.19
  • Published : 2018.09.30
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Abstract

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

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References

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