• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1258-1261
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• 2004

Degradation phenomenon in the low-temperature polysilicon (LTPS) thin-film transistors (TFTs) with different junction structures was investigated. A gate-overlapped lightly doped drain (GOLDD) structure showed better hot-carrier stress (HCS) stability than a conventional LDD one. On the other hand, high drain current stress (HDCS) at $V_{gs}$ = $V_{ds}$ conditions caused much severe device degradation in the GOLDD structure because of its higher current level resulting in the higher applied power. It is suggested that self-heating-induced mobility degradation in the GOLDD TFFs be suppressed for using this structure in short-channel devices.

• ETRI Journal
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• v.20 no.2
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• pp.241-249
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• 1998

The structure and electrical characteristics of metal-ferroelectric-semiconductor FET(MFSFET) for a single transistor memory are presented. The MFSFET was comprised of polysilicon islands as source/drain electrodes and $BaMgF_4$ film as a gate dielectric. The polysilicon source and drain were built-up prior to the formation of the ferroelectric film to suppress a degradation of the film due to high thermal cycles. From the MFS capacitor, the remnant polarization and coercive field were measured to be about $0.6{\mu}C/cm^2$ and 100 kV/cm, respectively. The fabricated MFSFETs also showed good hysteretic I-V curves, while the current levels disperse probably due to film cracking or bad adhesion between the film and the Al electrode.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.176-184
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• 1996

To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.9
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• pp.371-377
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• 2003

We perform the physical analysis such that Si/W composition ratios and phosphorus distribution change in the W/S $i_{x}$ thin films according to phosphorus concentration of polysilicon and W $F_{6}$ flow rate for the formation of WS $i_{x}$ polycide used as a gate electrode. We report that these physical characteristics have effects on the contact resistance between word line and bit line in DRAM devices. RBS measurements show that for the samples having phosphorus concentrations of 4.75 and 6.0${\times}$10$^{2-}$ atoms/㎤ in polysilicon, by applying W $F_{6}$ flow rates decreases from 4.5 to 3.5 sccm, Si/W composition ratio has increases to 2.05∼2.24 and 2.01∼2.19, respectively. SIMS analysis give that phosphorus concentration of polysilicon for both samples have decreases after annealing, but phosphorus concentration of WS $i_{x}$ thin film has increases by applying W $F_{6}$ flow rates decreases from 4.5 to 3.5 sccm. The contact resistance between word line and bit line in the sample with phosphorus concentration of 6.0 ${\times}$ 10$^{20}$ atoms/㎤ in polysilicon is lower than the sample with 4.75 ${\times}$ 10$^{20}$ atoms/㎤ After applying W $F_{6}$ flow rates decreases from 4.5 to 3.5 sccm, the contact resistance has been improved dramatically from 10.1 to 2.3 $\mu$ $\Omega$-$\textrm{cm}^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.362-364
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• 2016

본 논문에서는 MOS(Metal Oxide Semiconductor) Capacitor의 산화막내에 다양한 원인에 의해 존재하는 비이상적인 전하들 중 Fixed Oxide Charge가 소자의 문턱전압에 어떤 영향을 주는지 분석했다. 분석한 결과 n+ polysilicon Gate를 가지고, 산화막인 $SiO_2$의 두께가 3nm이고, 도핑농도가 $10^{18}cm^{-2}$인 P형 실리콘 기판으로 이루어진 MOS Capacitor에서 Fixed Oxide Charge Density가 $C/cm^2$ 이상일 때 문턱전압을 0.01V 이상 감소시키고 $C/cm^2$ 이하일 때 문턱전압을 0.01V 이상 증가시켰다.

• Journal of Electrical Engineering and information Science
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• v.2 no.4
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• pp.106-110
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• 1997

A new SOI NMOSFET with a 'LOCOS-like' shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication was tried. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3${\mu}{\textrm}{m}$ SOI devices with V\ulcorner of 0.77V and Tox=7.6nm is 360$mutextrm{A}$/${\mu}{\textrm}{m}$ at V\ulcorner\ulcorner=3.5V and V\ulcorner=2.5V. Improved breakdown characteristics were obtained and the BV\ulcorner\ulcorner\ulcorner(the drain voltage for 1 nA/${\mu}{\textrm}{m}$ of I\ulcorner at V=\ulcorner\ulcorner=0V) of the device with L\ulcorner\ulcorner=0.3${\mu}{\textrm}{m}$ under the floating body condition was as high as 3.7 V. Problems for the new scheme are also addressed and more advanced device structure based on the proposed scheme is proposed to solve the problems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.96-106
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• 1996

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.915-918
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• 2007

We have grown $SiO_2$ film on a polycrystalline Si layer using excited ozone gas, which is produced by ultra-violet light irradiation to ozone gas, without heating substrate. The obtained $SiO_2$ film shows dielectric properties comparable to the device quality films measured at the MIS capacitor configuration.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.6
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• pp.83-88
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• 1985

An electrically alterable read only memory with polysilicon gate is experimently realized employing a SONOS structure. The SONOS memory cells are proposed to achieve lower programming voltage with thin nitride (70A, 170$\AA$) layer. Its programming voltage is 10V (Tnit=70$\AA$), 22V(Tnit=170$\AA$). And the SONOS cell is able to, erasc biasing negative gate pulse, then its voltage is about -24V for nitride thickness of 170$\AA$.