• Title/Summary/Keyword: polycrystalline silicon

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The microstructure of polycrystalline silicon thin film that fabricated by DC magnetron sputtering

  • Chen, Hao;Park, Bok-Kee;Song, Min-Jong;Park, Choon-Bae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.332-333
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    • 2008
  • DC magnetron sputtering was used to deposit p-type polycrystalline silicon on n-type Si(100) wafer. The influence of film microstructure properties on deposition parameters (DC power, substrate temperature, pressure) was investigated. The substrate temperature and pressure have the important influence on depositing the poly-Si thin films. Smooth ploy-Si films were obtained in (331) orientation and the average grain sizes are ranged in 25-30nm. The grain sizes of films deposited at low pressure of 10mTorr are a little larger than those deposited at high pressure of 15mTorr.

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Characterization of Thin $SiO_2/Si_3N_4$ Film on $WSi_2$ (텅스텐 실리사이드 상의 얇은 $SiO_2/Si_3N_4$ 막의 특성 평가)

  • 구경원;홍봉식
    • Journal of the Korean Vacuum Society
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    • v.1 no.1
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    • pp.183-189
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    • 1992
  • The characteristics of N/O(SiOz/SisN4) film on WSi2 are compared with storage node Poly-Si. Leakage current and breakdown voltage are improved and storage capacitance is decreased. The oxidation rate of WSiz is more rapid than polycrystalline silicon. Thus the thick bottom oxide on the WSiz causes to the decrease of capacitance. The out diffusion of dopant impurity in polycrystalline silicon through the silicide leads to the formation of a depletion region in the polycrystalline silicon and the decrease of depletion capacitance. That results in the decrease of the overall storage capacitance.

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Fabrication and Characterization of Polycrystalline Silicon Solar Cells using Preferential Etching of Grain Boundaries (결정입계의 선택적 식각을 이용한 다결정 규소 태양전지의 제작과 특성)

  • Kim, Sang-Su;Kim, Cheol-Su;Lim, Dong-Gun;Kim, Do-Young;Yi, Jun-Sin
    • Proceedings of the KIEE Conference
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    • 1997.07d
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    • pp.1430-1432
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    • 1997
  • A solar cell conversion effiency was degraded by grain boundary effect in polycrystalline silicon. To reduce these effects of the grain boundaries, we investigated various influencing factors such as preferential chemical etching of grain boundaries, grid design, transparent conductive thin film, and top metallization along grain boundaries. Pretreatment in $N_2$ atmosphere and gettering by $POCl_3$ and Al were performed to obtain polycrystalline silicon of the reduced defect density. Structural, electrical, and optical properties of solar cells were characterized. Improved conversion efficiencies of solar cell were obtained by a combination of Al diffusion into grain boundaries on rear side, fine grid finger, top Yb metal grid on Cr thin film of $200{\AA}$ and buried contact metallization along grain boundaries.

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Crystal Growth of Polycrystalline Silicon by Directional Solidification (일방향 응고법에 의한 단결정 Si의 결정성장에 관한 연구)

  • 김계수;이창원;홍준표
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.3 no.2
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    • pp.149-156
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    • 1993
  • Polycrystalline silicon was produced from metallurgical-grade Si by unidirectional solidification. Variations of impurity concentration and resistivity in the ingots have been investigated. X-ray diffraction analysis has also been performed to examine the crystal orientation. According to the X-ray diffraction analysis on the polycrystalline silicon, preferential orientation was changed from ( 220) into ( III ) with decreasing growth rate. Also, with increasing growth rate and fraction solidified, the resistivity tends to decrease.

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Characteristics of Excimer Laser-Annealed Polycrystalline Silicon on Polymer layers (폴리머 위에 엑시머 레이저 방법으로 결정화된 다결정 실리콘의 특성)

  • Kim, Kyoung-Bo;Lee, Jongpil;Kim, Moojin;Min, Youngsil
    • Journal of Convergence for Information Technology
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    • v.9 no.3
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    • pp.75-81
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    • 2019
  • In this work, we investigated a low temperature polycrystalline silicon (LTPS) thin film transistors fabrication process on polymer layers. Dehydrogenation and activation processes were performed by a furnace annealing at a temperature of $430^{\circ}C$ for 2 hr. The crystallization of amorphous silicon films was formed by excimer laser annealing (ELA) method. The p-type device performance, fabricated by polycrystalline silicon (poly-Si) films, shows a very good performance with field effect mobility of $77cm^2/V{\cdot}s$ and on/off ratio current ratio > $10^7$. We believe that the poly-Si formed by a LTPS process may be well suited for fabrication of poly-Si TFTs for bendable panel displays such as AMOLED that require circuit integration.

Ultra low temperature polycrystalline silicon thin film transistor using sequential lateral solidification and atomic layer deposition techniques

  • Lee, J.H.;Kim, Y.H.;Sohn, C.Y.;Lim, J.W.;Chung, C.H.;Park, D.J.;Kim, D.W.;Song, Y.H.;Yun, S.J.;Kang, K.Y.
    • 한국정보디스플레이학회:학술대회논문집
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    • 2004.08a
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    • pp.305-308
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    • 2004
  • We present a novel process for the ultra low temperature (<150$^{\circ}C$) polycrystalline silicon (ULTPS) TFT for the flexible display applications on the plastic substrate. The sequential lateral solidification (SLS) was used for the crystallization of the amorphous silicon film deposited by rf magnetron sputtering, resulting in high mobility polycrystalline silicon (poly-Si) film. The gate dielectric was composed of thin $SiO_2$ formed by plasma oxidation and $Al_2O_3$ deposited by plasma enhanced atomic layer deposition. The breakdown field of gate dielectric on poly-Si film showed above 6.3 MV/cm. Laser activation reduced the source/drain resistance below 200 ${\Omega}$/ㅁ for n layer and 400 ${\Omega}$/ㅁ for p layer. The fabricated ULTPS TFT shows excellent performance with mobilities of 114 $cm^2$/Vs (nMOS) and 42 $cm^2$/Vs (pMOS), on/off current ratios of 4.20${\times}10^6$ (nMOS) and 5.7${\times}10^5$ (PMOS).

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Polycrystalline silicon thin film fabricated on plastic substrates by excimer laser annealing (엑시머 레이저 어닐링을 이용하여 플라스틱 기판에 형성한 다결정 실리콘 박막의 특성)

  • 조세현;이인규;김영훈;문대규;한정인
    • Journal of the Korean Vacuum Society
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    • v.13 no.1
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    • pp.29-33
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    • 2004
  • In this paper, we investigated the ultra-low temperature(<$150^{\circ}C$) polycrystalline silicon film on plastic substrate application using RF-magnetron sputtering and excimer laser annealing. Amorphous silicon films were deposited using Ar/He mixture gas at $120^{\circ}C$ and in-film argon concentration was less than 2%, which was measured to Rutherford Backscattering Spectrometry. At energy density 320mJ/$\textrm{cm}^2$, RMS roughness was 267$\AA$ and UV crystallinity was 62%. The grain size varies from 50nm to 100nm after excimer laser irradiation.

Thin film solar cells (박막형 태양전지)

  • 김동섭;이수홍
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.5 no.1
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    • pp.67-77
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    • 1995
  • Abstract The principal factor affecting the increased penetration of photovoltaics into the marketplace is cost. For traditional crystalline silicon modules, half of the cost is that of the silicon wafers. As a result much effort has centered on reducing this cost by the use of thin film technologies. Substantial technical progress has been made towards improving the efficiencies of polycrystalline thin film solar cells to reduce the production costs. Progress in semiconductor deposition techniques has also been rapid. The most mature of these are based on polycrystalline silicon (p - Si), amorphous silicon (a - Si), copper indium diselenide $SuInSe_2$(CIS), and cadmium telluride (CdTe). This paper explores the recent advances in the development of polycrystalline thin film solar cells.

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Performance of Thin Film Transistors Having an As-Deposited Polycrystalline Silicon Channel Layer

  • Hong, Wan-Shick;Cho, Hyun-Joon;Kim, Tae-Hwan;Lee, Kyung-Min
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08b
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    • pp.1266-1269
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    • 2007
  • Polycrystalline silicon (poly-Si) films were prepared directly on plastic substrates at a low (< $200^{\circ}C$) by using Catalytic Chemical Vapor Deposition (Cat-CVD) technique without subsequent annealing steps. Surface roughness of the poly-Si layer and the density of the gate dielectric layer were found to be influential to the TFT performance.

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