• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.1131-1134
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• 2003

A low temperature doping technique has been studied for application in poly-Si TFT's on plastic substrates. Heavily-doped amorphous silicon layers were deposited on poly-Si and the dopant atoms were driven in by subsequent excimer laser annealing. The entire process was carried out under a substrate temperature of $120^{\circ}C$, and a sheet resistance as low as $300 {\Omega}/sq$. was obtained.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.790-792
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• 2005

In this work we attempted to find the origin of brightness non-uniformity in SLS poly-Si TFT AMOLED. By developing a suitable SLS process with a compensation circuit, we have successfully improved the non-uniformity from 40% to 1.7%. We could fabricate 2.2" AMOLED display using SLS poly-Si.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.8
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• pp.365-370
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• 2001

We have proposed and fabricated a new poly-Si TFT employing air-cavities at the edges of gate oxide in order to reduce the vertical electric field induced near the drain due to low dielectric constant of air. Air-cavity has been successfully fabricated by employing the wet etching of gate oxide and APCVD (Atmospheric pressure chemical vapor deposition) oxide deposition. Our experimental results show that the leakage current of the proposed TFT is considerably reduced by the factor of 10 and threshold voltage shift under high gate bias is also reduced because the carrier injection into gate insulator over the drain depletion region is suppressed.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.857-859
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• 1999

본 연구에서는 Poly-Si TFT-LCD 패널에 내장할 수 있는 새로운 방식의 디지털 데이터 구동회로를 설계하였는데, 제안된 데이터 구동회로의 특징 및 장점을 요약하면 다음과 같다. 첫째, 단순한 구조의 샘플드램프 D/A Conversion 회로로 구성되어 회로가 복잡하지 않고, 소요되는 TFT의 수가 적으며, 패널의 스캔방식(Inversion Method : Row/Column/Dot)을 쉽게 선택할 수 있다. 둘째, 기존의 디지털 데이터 구동회로와는 달리, D/A Conversion을 위해 필요한 기준 전압원의 수가적어 입력 핀 수를 적게 가져갈 수 있다. 셋째, Ramp 신호의 조정에 의해 감마 보정 등을 포함한 데이터의 에러에 대한 보정이 수월하다. 넷째, 라인 스친 방식으로 구동하므로 기존의 샘플 앤 홀드방식의 아날로그 구동회로에 비해 화소 데이터의 시간적 안정성을 충분히 확보할 수 있다.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.212-222
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• 1992

To use polycrystalline Si Thin Film Transistor (poly-Si TFT) in high density SRAM instead of High Load Resistor (HLR), TFT is needed to show good electrical characteristics such as large carrier mobility, low leakage current, high driver current and low subthreshold swing. To satisfy these electrical characteristics, the trap state density must be reduced in the channel poly. Technological issues pertinent to the channel poly fabrication process are investigated and discussed. They are solid phase growth (SPG), Si-ion implantation, laser annealing and hydrogenation. The electrical properties of several CVD oxides used as the gate oxide of TFT are compared. The dependence of the electrical characteristics of TFT on source-drain ion-implantation dose, drain offset length and dopant lateral diffusion are also described.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1751-1753
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• 2000

다결정 실리콘 박막 트랜지스터 (poly-Si TFT)의 누설전류를 억제하기 위해 게이트 절연막(gate oxide)의 가장자리에 캐비티(cavity)를 가지는 새로운 구조의 다결정 박막 트랜지스터를 제안하였다. 캐비티는 드레인(drain) 공핍영역(depletion region) 위에 형성되어 드레인 주변에 유도되는 수직전계를 감소시켜 누설전류를 억제하고 소자의 안정성을 향상시킬 수 있다. 본 연구에서 제작된 poly-Si TFT는 기존의 TFT에 비해 온-오프 전류비가 향상되었고 전기적 스트레스 후의 문턱전압 변화가 작음을 확인하였다.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3084-3087
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• 2000

본 논문은 대면적 Poly-Si TFT-LCD 구동회로의 면적을 줄이기 위한 효율적인 구동방식을 제안한다. 구체적으로 화소의 충전 시간을 줄이기 위한 화면 수평 분할 구동방식과 데이터 라인 프리차징 방식을 제안한다. 또한 수평분할 구동을 위한 Bit-Reduced R-DAC를 제안한다. 마지막으로 본 논문에서는 제안하는 구동 방식을 14 1" XGA 6-bit 일체형 디지털 Poly-Si TFT-LCD 구동회로에 적용하여 효용성을 검증한다 시뮬레이션 결과 계조별 평균 구동오차는 14mv로서 1/2 LSB(${\risingdotseq}$23mV) 정확도 요구 조건을 만족한다. 데이터 드라이버의 폭은 상 하단 각각 약 6mm이며 이는 기존 설계에 비해 66% 감소한 값이다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.53-58
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• 1998

A buried channel poly-Si TFT (BCTFT) for application of high performance integrated circuits has been proposed and fabricated. BCTFT has unique features, such as the moderately-doped buried channel and counter-doped body region for conductivity modulation, and the fourth terminal entitled back bias for preventing kink effect. The n-type and p-type BCTFT exhibits superior performance to conventional poly-Si TFT in ON-current and field effect mobility due to moderate doping at the buried channel. The OFF-state leakage current is not increased because the carrier drift is suppressed by the p-n junction depletion between the moderately-doped buried channel and the counter-doped body region.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.118-119
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• 2007

High performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide semiconductor (CMOS) inverters with a high quality laser crystallized channel were fabricated. Low temperature crystallization methods of a-Si film using the excimer-laser annealing (ELA) and sequential lateral solidification (SLS) were performed. The NMOS thin-film-transistor (TFT) at lower layer of CMOS was fabricated on oxidized bulk Si substrate, and the PMOS TFT at upper layer of CMOS was fabricated on interlayer dielectric film. The 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and was enough for the vertical integrated CMOS applications.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.198-201
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• 2006

The optimization of poly-Si TFT process on metal foil for UTL AMOLED was systematically investigated. The improvement in device performance of poly-Si TFT on metal foil was achieved by optimizing the dopant activation condition and gate dielectric structure. Hence, the world first flexible full color 5.6-inch AMOLED with top emission mode on poly-Si TFT stainless steel foil is demonstrated.