• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.3
• /
• pp.206-211
• /
• 2005

The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.

• Information Display
• /
• v.5 no.1
• /
• pp.25-30
• /
• 2004

Poly-Si TFT(Thin Film Transistor) technology are reviewed and discussed. Poly-Si TFTs fabricated on glass using low-temperature process were studied extensively for the application to LCD (Liquid Crystal Display) as well as to OLED(Organic Light Emitting Diode) Display. Currently, one of the application targets of the poly-Si TFT is emphasized on the highly functional SOG(System on Glass). Improvement of device characteristics such as an enhancement of carrier mobility has been studied intensively by enlarging the grain size. Reduction of the voltage and shrinkage of the device size are the trend of AM FPD(Active Matrix Flat Panel Display) as well as of Si LSI, which will arise a peculiar issue of uniformity for the device performance. Some approaches such as nucleation control of the grain seed or lateral grain growth have been tried, so far.

• Proceedings of the KSME Conference
• /
• 2007.05a
• /
• pp.1455-1458
• /
• 2007

In this research, a polycrystalline silicon (poly-Si) film layer for micro thermoelectric generator (TEG) was fabricated. The fabrication process of the thermoelectric poly-Si film layer is explained. The P-type and N-type poly-Si films were fabricated on a tetra ethoxy silane (TEOS) layer with a supporting Si wafer. Seebeck coefficient and electrical conductivity were measured, including the transport properties such as the hall coefficient, hall mobility and carrier concentration. The design parameters for a rapid thermal process (RTP) were decided based on the experimental results. The measured power factors of the P-type and N-type were $21.2\;{\mu}Wm^{-1}K^{-2}$ and $26.7\;{\mu}Wm^{-1}K^{-2}$, respectively.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.34D no.4
• /
• pp.33-39
• /
• 1997

The crystallization temperature of an amorphous silicon (a-Si) can be lowered down to 400.deg. C by a new method : Double-metal induced lateral crystallization (DMILC). The a-Si film was laterally crystallized from Ni and Pd deposited area, and its lateral crystallization rate reaches up to 0.2.mu.m/hour at that temperature and depends on the overlap length of Ni and Pd films; the shorter the overlap length, the faster the rate. Poly-Silicon thin film transistors (poly-Si TFT's) fabricated by DMILC at 400.deg. C show a field effect mobility of 38.5cm$^{3}$/Vs, a minimum leakage current of 1pA/.mu.m, and a slope of 1.4V/dec. The overlap length does not affect the characteristics of the poly-Si TFT's, but determines the lateral crystallization rate.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2002.08a
• /
• pp.523-525
• /
• 2002

The poly-Si thin film can be used in high mobility active matrix liquid-crystal display (AMLCD) and system on panel (SOP). In this paper, poly-Si thin films were grown by novel high temperature process on the molybdenum (Mo) substrate. By applying a high current above 48A on a Mo substrate. We obtained an improved crystalline Si films with the crystallinity over 80%. We exhibit the properties of structural and electrical properties of high temperature poly-Si thin film transistor on the Mo substrates.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.5
• /
• pp.367-372
• /
• 1999

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.445-446
• /
• 2005

This letter reports the fabrication of polycrystalline silicon thin-film transistors (poly-Si TFT) on flexible plastic substrates using amorphous silicon (a-Si) precursor films by sputter deposition. The a-Si films were deposited with mixture gas of argon and helium to minimize the argon incorporation into the film. The precursor films were then laser crystallized using XeCl excimer laser irradiation and a four-mask-processed poly-Si TFTs were fabricated with fully self-aligned top gate structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.04a
• /
• pp.62-63
• /
• 2006

In this paper, the characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) fabricated on polymer substrates are investigated. The a-Si films was laser annealed by using a XeCl excimer laser and a four-mask-processed poly-Si TFT was fabricated with fully self-aligned top gate structure. The fabricated nMOS TFT showed field-effect mobility of $30cm2/V{\cdot}s$, on/off ratio of 105 and threshold voltage of 5 V.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1999.11a
• /
• pp.67-67
• /
• 1999

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.3
• /
• pp.233-237
• /
• 2002

A giga-bit DRAM(dynamic random access memory) technology with W/WNx/poly-Si dual gate electrode is presented in 7his papers. We fabricated $0.16\mu\textrm{m}$ CMOS using this technology and succeeded in suppressing short-channel effects. The saturation current of nMOS and surface-channel pMOS(SC-pMOS) with a $0.16\mu\textrm{m}$ gate was observed 330 $\mu\A/\mu\textrm{m}$ and 100 $\mu\A/\mu\textrm{m}$ respectively. The lower salutation current of SC-pMOS is due to the p-doped poly gate depletion. SC-pMOS shows good DIBL(dram-induced harrier lowering) and sub-threshold characteristics, and there was no boron penetration.