• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.339-344
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• 2017

A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.3
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• pp.540-547
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• 1994

Contact and frictional locking conditions and the effect of shielding due to contact at the facet, which could be represented by the difference in energy release rate, as a function of phase angle of loading are analyzed in this study for the case of interfacial cracks by assuming single crack-kink model. The analysis of contact effects on interfacial fracture resistance shows that relative shielding increases as the shear component was increased, which indicates a qualitative agreement with the previous experimental results.

• Proceedings of the Optical Society of Korea Conference
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• 2009.10a
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• pp.241-242
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• 2009

Characterics of carrier-envelope-offset frequency ($f_{ceo}$) of a femtosecond laser stabilized by the direct locking method were investigated using two f-to-2f interferometers. The stability of $f_{ceo}$ was comaparable to that achieved with a conventional PLL method.

• 한국금형공학회:학술대회논문집
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• 2008.06a
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• pp.159-162
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• 2008

High pressure is involved during injection molding operation specially packing phase. Cracks in the mold are often occurred by high cavity pressure. In this study, structural analysis of mold has been performed using commercial softwares, Abaqus and Ansys, to investigate cause of crack in the injection mold. Structural analysis contains four cases: stress distribution according to the cavity pressure, stress concentration according to the boundary conditions, stress concentration for inter-locking design of mold, and stress concentration for distributed cavity pressure. Through this study it was observed that the locations of stress concentrations were coincident with locations of crack. Robust mold design is being required to withstand high cavity pressure.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2008.05a
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• pp.297-300
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• 2008

High pressure is involved during injection molding operation specially packing phase. Cracks in the mold are often occurred by high cavity pressure. In this study, structural analysis of mold has been performed using commercial softwares, Abaqus and Ansys, to investigate cause of crack in the injection mold. Structural analysis contains four cases: stress distribution according to the cavity pressure, stress concentration according to the boundary conditions, stress concentration for inter-locking design of mold, and stress concentration for distributed cavity pressure. Through this study it was observed that the locations of stress concentrations were coincident with locations of crack. Robust mold design is being required to withstand high cavity pressure.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10a
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• pp.326-328
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• 1999

지리정보시스템(GIS) 클라이언트는 Open API를 이용한 개방형 구조를 지향하고 있다. OLE DB는 OLE/COM을 기반으로 다양한 데이터 소스에 대한 표준 인터페이스를 제공하기 때문에 서로 다른 데이터 소스에 대한 상호운용성을 지원하는 것이 용이하다. 그러나 OLE DB를 이용하여 공간 데이터를 수정하는 경우에 Two-Phase Locking 방식으로 인한 긴 대기시간(Long Wait)과 set 단위의 locking을 지원하지 않는 문제가 발생한다. 본 논문은 OLE DB를 이용한 공간데이터의 수정을 위하여 Row 단위의 잠금이 아닌 Rowset 단위의 영역잠금을 위한 잠금 모드와 인터페이스를 정의한다. 그리고 긴 대기시간을 해결하고 동시성을 높이기 위해 동시수정 트랜잭션 인터페이스를 정의하고 프로토콜을 제시한다.

• ETRI Journal
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• v.34 no.4
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.287-292
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• 2016

A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from $2^{31}-1$ PRBS input data has 0.011-UI rms jitter.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.107-113
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• 2014

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.10
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• pp.1163-1171
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• 2007

In this paper, the design techniques required to design heterodyned OPLL such as frequency-phase deference detector, loop filter and phase noise of semiconductor laser are presented. Through the experiments with the calculated parameters, we confirmed that the frequency-phase difference detector simply develops an error component that is proportional to the frequency-phase difference between heterodyned optical signals. The achieved frequency-phase locking range of the input laser diode frequency is around ${\pm}150MHz$. This paper describes the details of the designed as well as experimental results.