Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A Design of Voltage Controlled Oscillator and High Speed 1/4 Frequency Divider using 65nm CMOS Process

65nm CMOS 공정을 이용한 전압제어발진기와 고속 4분주기의 설계

  • Lee, Jongsuk (School of Electronic Engineering, Soongsil University) ;
  • Moon, Yong (School of Electronic Engineering, Soongsil University)
  • 이종석 (숭실대학교 정보통신전자공학부) ;
  • 문용 (숭실대학교 정보통신전자공학부)
  • Received : 2014.08.10
  • Accepted : 2014.10.28
  • Published : 2014.11.25
Download PDF
⟨ Previous Next ⟩

Abstract

A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

60GHz 무선 통신 시스템에 적용 가능한 전압 제어 발진기와 고속 4분주기를 65nm CMOS 공정을 사용하여 설계했다. 전압제어 발진기는 전류소스와 NMOS 차동쌍 LC구조로 설계하였으며 분주기는 차동 인젝션 록킹 구조에 베렉터를 추가하여 동작주파수 범위를 조절할 수 있는 구조로 설계했다. 전압 제어 발진기와 분주기에 모두 전류소스를 추가하여 전원잡음에 따른 위상잡음 특성을 개선하였다. 전압 제어 발진기는 64.36~67.68GHz의 동작범위가 측정됐고, 고속 4분주기는 전압 제어 발진기의 동작범위에 대해 정확한 4분주가 가능하며 5.47~5.97dBm의 높은 출력전력이 측정됐다. 분주기를 포함한 전압제어 발진기의 위상잡음은 1MHz 오프셋 주파수에서 -77.17dBc/Hz이고 10MHz 오프셋 주파수에서 -110.83dBc/Hz이다. 소모전력은 전원전압 1.2V에서 38.4mW 이다 (VCO 포함).

Keywords

References

  1. M.-W. Li, H.-C. Kuo, T.-H. Huang, and H.-R. Chuang, "60 GHz CMOS divide-by-5 injectionlocked frequency divider with an open-stubloaded floating-source injector," IEEE RFIC Symp., pp. 1-4, Jun. 2011.
  2. I.-Ting Lee, Chiao-Hsing Wang, Chun-Lin Ko, Ying-Zong Juang and Shen-Iuan Liu, "A 3.6 mW 125.7-131.9 GHz Divide-by-4 Injection-Locked Frequency Divider in 90 nm CMOS," IEEE, LMWC, vol. 22, no. 3, pp.132-134, Feb. 2012.
  3. Yanping Ding and Kenneth K. 0, "A Low-Power 17-GHz 256/257 Dual-Modulus Prescaler Fabricated in a 130-nm CMOS Process," IEEE, RFIC Symp., pp. 456-468, Jun. 2005.
  4. H.-D. Wohlmuth and D. Kehrer, "A 15 GHz 256/257 Dual-Modulus Prescaler in 120 nm CMOS," IEEE, ESSCIRC, pp.77-80, Sept. 2003.
  5. Seong-Yong Jang et.al., "Analysis of Quality factor and Effective inductance of Inductor for RF Integrated Circuits in 90nm CMOS Technology," Journal of The Institute of Electronics Engineers of Korea, Vol.50, No.5, pp.128-133, May. 2013. https://doi.org/10.5573/ieek.2013.50.5.128
  6. Lianming Li, Patrick Reynaert and Michiel Steyaert, "A 60GHz 15.7mW static frequency divider in 90nm CMOS," IEEE, ESSCIRC, pp.246- 249, Sep. 2010.
  7. Hsieh-Hung Hsieh, Huan-Sheng Chen and Liang- Hung LuA, "V -Band Divide-by-4 Direct Injection- Locked Frequency Divider in 0.18-${\mu}m$ CMOS," IEEE, E Trans. Microw. Theory Tech., vol. 59, no. 2, pp.393-405, Feb. 2010.
  8. Ho-Gil Kim and Sang-Hoon Chai, "Design of 26GHz Variable-N Frequency Divider for RF PLL," Journal of The Institute of Electronics Engineers of Korea, Vol.49, No.9, pp.270-276, Sep. 2012. https://doi.org/10.5573/ieek.2012.49.9.270
  9. Chang-Ryong Heo and Chong-Suck Rim, "Decoupling Capacitance Allocation at the Floorplan Level for Power Supply Noise Reduction," Journal of The Institute of Electronics Engineers of Korea, Vol.42, No.9, pp.270-276, Sep. 2005.