• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.122-133
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• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.195-200
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• 2015

This paper presents SVBS-TDC (Semi-Vernier Binary-Search Time-to-Digital Converter) for the noise improvement of ADPLL (All-Digital Phase Locked Loop. We used a Semi-Vernier BS-TDC (Binary-Search TDC) architecture to improve the operation speed more then 10 times compared with the previous conventional BS-TDC and ensured a 510ps wide input range. The proposed Semi-Vernier BS-TDC was designed in a 65ns CMOS process and the simulation results showed 200MHz speed and 4ps resolution with a 1.2V supply voltage, and considerable noise improvement of ADPLL.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.100-105
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• 2010

In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.5
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• pp.677-684
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• 2021

This paper presents a time-to-digital converter for measuring absolute time differences. The time-to-digital converter was designed and fabricated in 0.18-um CMOS technology and it can be applied to Light Detection and Ranging system which requires long time-cover range and 50ps time resolution. Since designed time-to-digital converter adopted the reference clock of 625MHz generated by phase locked loop, it could have absolute time resolution of 50ps after automatic calibration and its cover range was over than 800ns. The time-to-digital converter adopted a counter and chain delay lines for time measurement. The counter is used for coarse time measurement and chain delay lines are used for fine time measurement. From many times experiments, fabricated time-to-digital converter has 50 ps time resolution with maximum INL of 0.8 LSB and its power consumption is about 70 mW.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.6
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• pp.1023-1030
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• 2023

FMCW LiDAR system with robust target detection capabilities even under adverse operating conditions such as snow, rain, and fog is addressed in this paper. Our focus is primarily on enhancing the performance of FMCW LiDAR by improving the characteristics of the frequency-modulated laser, which directly influence range resolution, coherence length, and maximum measurement range etc. of LiDAR. We describe the utilization of an unbalanced Mach-Zehnder laser interferometer to measure real-time changes of the lasing frequency and to correct frequency modulation errors through an optical phase-locked loop technique. To extend the coherence length of laser, we employ an extended-cavity laser diode as the laser source and implement a laser interferometer with an photonic integrated circuit for miniaturization of optical system. The developed FMCW LiDAR system exhibits a bandwidth of 10.045GHz and a remarkable distance resolution of 0.84mm.

• Proceedings of the Optical Society of Korea Conference
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• 2002.07a
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• pp.68-69
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• 2002

두 대의 결맞은 레이저는 원자의 고분해 분광이나 광통신 등의 여러 분야에서 응용이 가능하다. 본 연구에서는 세슘 원자분수 주파수표준기와 저속 원자빔 주파수표준기에서 원자의 속도 선택 실험에 사용하기 위한 9.2 GHz의 주파수 차이를 가지는 두 대의 결맞은 레이저를 제작하였다. 결맞은 레이저는 주입 잠금(injection locking)이나 위상 잠금 회로(phase locking loop)를 이용하여 만들 수 있다. (중략)

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.955-958
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• 1999

We designed a phase locked loop (PLL), which is applicable to microprocessor clock generation application. The designed PLL has a new simple phase frequency detector (PFD) which eliminate dead-zone and has a good high frequency characteristic. The lock-in range of the designed PLL is 50 MHz ~ 150 MHz at 3.3v power supply voltage. The design is carried out using a 0.6${\mu}{\textrm}{m}$ triple metal CMOS process. The area of the layout is 0.35mm by 0.42mm with 359 transistors.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.246-248
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• 2007

This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-${\mu}m$ CMOS process, and 1.8v supply voltage, and 25MHz of input oscillator frequency, and 800MHz of output frequency and is simulated by using ADE of Cadence.