Browse > Article
http://dx.doi.org/10.5573/ieek.2013.50.2.122

An Offset and Deadzone-Free Constant-Resolution Phase-to-Digital Converter for All-Digital PLLs  

Choi, Kwang-Chun (Department of Electrical and Electronic Engineering, Yonsei University)
Kim, Min-Hyeong (Department of Electrical and Electronic Engineering, Yonsei University)
Choi, Woo-Young (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.2, 2013 , pp. 122-133 More about this Journal
Abstract
An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.
Keywords
ADPLL; PFD; TDC; PDC;
Citations & Related Records
연도 인용수 순위
  • Reference
1 R. C. -H. Chang, H. -M. Chen and P. -J. Huang, "A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/ Frequency Detector", IEEE Trans. Circuits and Systems I: Reg. Papers, Vol. 55, No. 9, pp. 2483-2490, Oct. 2008.   DOI   ScienceOn
2 B. -G. Kim and L. -S. Kim, "A 250-MHz-2-GHz Wide-Range Delay-Locked Loop", IEEE J. Solid-State Circuits, Vol. 40, No. 6, pp. 1310-1321, Jun. 2005.   DOI   ScienceOn
3 J. S. Lee, W. K. Jin, D. M. Choi, G. S. Lee and S. Kim, "A WIDE RANGE PLL FOR 64X SPEED CD-ROMS & 10X SPEED DVD-ROMS", IEEE Trans. Consumer Electronics, Vol. 46, No. 3, pp. 487-493, Aug. 2000.   DOI   ScienceOn
4 M. Mansuri, D. Liu and C. -K. K. Yang, "Fast Frequency Acquisition Phase-Frequency Detectors for GSa/s Phase-Locked Loops", IEEE European Solid-State Circuits Conf., pp. 333-336, Sep. 2001.
5 K. -C. Choi, S. -W. Lee, B. -C. Lee and W. -Y. Choi, "A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector", IEEE Trans. Circuits and Systems II: Exp. Briefs, Vol. 59, No. 3, pp. 143-147, Mar. 2012.   DOI   ScienceOn
6 V. Kratyuk, P. -K. Hanumolu, U. Moon and K. Mayaram, "A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy", IEEE Trans. Circuits and Systems II: Exp. Briefs, Vol. 54, No. 3, pp. 247-251, Mar. 2007.   DOI   ScienceOn
7 J. Lin, B. Haroun, T. Foo, J. -S. Wang, B. Helmick, S. Randall, T. Mayhugh, C. Barr and J. Kirkpatrick, "A PVT Tolerant 0.18MHz to 600MHz Self-Calibrated Digital PLL in 90nm CMOS Process", IEEE Int. Solid-State Circuit Conf., pp. 488-541, Feb. 2004.
8 T. Olsson and P. Nilsson, "A Digitally Controlled PLL for SoC Applications", IEEE J. Solid-State Circuits, Vol. 39, No. 5, pp. 751-760, May. 2004.   DOI   ScienceOn
9 S. -Y. Lin and S. -I. Liu, "A 1.5 GHz All-Digital Spread-Spectrum Clock Generator", IEEE J. Solid-State Circuits, Vol. 44, No. 11, pp. 3111-3119, Nov. 2009.   DOI   ScienceOn
10 P. Dudek, S. Szczepanski and J. V. Hatfield, "A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line", IEEE J. Solid-State Circuits, Vol. 35, No. 2, pp. 240-247, Feb. 2000.   DOI   ScienceOn
11 J. Yu, F. F. Dai and R. C. Jaeger, "A 12-Bit Vernier Ring Time-to-Digital Converter in $0.13{\mu}m$ CMOS Technology", IEEE J. Solid-State Circuits, Vol. 45, No. 4, pp. 830-842, Apr. 2010.   DOI   ScienceOn
12 이형민, 신우열, N. Xing, 김선권, 심대용, 홍기문, 김수환, "Open-Loop Mode에서 동작하는 DLL을 사용한 고해상도 Time-to-Digital 변환기", 제 17 회 한국반도체학술대회, TP2-29, 2010년 2월
13 C. -S. Hwang, P. Chen and H. -W. Tsao, "A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme", IEEE Trans. Nuclear Science, Vol. 51, No. 4, pp. 1349-1352, Aug. 2004.   DOI   ScienceOn