• 전기전자학회논문지
• /
• 제17권4호
• /
• pp.544-549
• /
• 2013

본 논문은 CDR회로의 지터 감소를 위해 변형된 이진 위상검출기(뱅뱅위상 검출기- BBPD) 회로를 제안하였다. 제안된 PD는 하나의 에지를 사용함으로써 전압리플을 줄여, 제안한 PD를 적용하여 설계한 CDR회로는 감소된 지터 특성을 보였다. CMOS 0.13um 공정을 사용하여 설계하였고 제안한 위상검출기를 포함하는 클럭데이터 복원회로는 모의실험결과 16.9mW 전력소비에 peak-peak 지터는 10.96ps, rms 지터는 0.89ps을 보였다.

• 전기전자학회논문지
• /
• 제10권1호
• /
• pp.10-15
• /
• 2006

본 논문에서는 기준동작 클럭없이 데이터만으로 구현되는 반주기의 4x 오버샘플링 위상/주파수검출기를 이용한 클럭 데이터 복원회로에 대하여 서술하였다. 위상 및 주파수검출기는 4x 오버샘플링 기법을 이용하여 설계되었다. 위상검출기는 뱅뱅 제어방법에 의해, 주파수검출기는 로테이션방법에 의해 동작한다. 위상 및 주파수 검출기로부터 발생된 6개의 신호들은 전하펌프로 들어갈 전하량을 결정한다. VCO단은 4개의 차동 지연단으로 구성되고 8개의 클럭신호를 생성한다. 제안된 회로는 공급전압 1.8V, 0.18um MOCS 공정으로 설계 시뮬레이션되었다. 제안된 구조의 PD와 FD를 사용하여 25%의 넓은 트래킹 주파수 범위를 가진다.

• ETRI Journal
• /
• 제33권5호
• /
• pp.752-758
• /
• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
• /
• pp.2175-2178
• /
• 2005

During normal machine operation, partial discharge(PD) measurements were performed with turbine generator analyzer(TGA) in five high voltage motors(rated 6.6kV). These high voltage motors were installed with 80pF capacitive couplers at the terminal box. The PD patterns were displayed two dimensional and three dimensional. TGA summarizes each plot with two quantities such as the normalized quantity number(NQN) and the peak PD magnitude(Qm). Off-line PD measurements were conducted on five motors. These motors were energized to 3.81kV. The PD levels in pC were measured with a conventional digital PD detector. The comparison of positive to negative PD indicates whether the defect elements of PD are within the insulation or on the insulation surface. Internal discharges were generated in phase A, B and C of COP-B and pulv.-B, in phase B of Pulv. C and in phase C of Pulv.-D motor. Discharge at conductor surface was discovered in phase A of Pulv. D motor. Slot discharges occurred in three phases of Pulv. E motor.

• 한국콘텐츠학회논문지
• /
• 제10권2호
• /
• pp.72-80
• /
• 2010

본 논문에서는 다중점 위상검출기(Phase detector: PD)를 이용한 1Gbps 클럭 및 데이터 복원(Clock and data recovery: CDR)회로를 제안한다. 제안된 위상검출기는 데이터의 천이 모서리와 클럭의 상승/하강 모서리 3점을 비교하여 up/down 신호를 생성한다. 기존의 위상검출기 회로는 클럭 주기의 배수 만큼의 up/down 펄스폭을 갖는 출력으로 전압제어발진기(Voltage controlled oscillator: VCO)를 조절하는 펄스폭변조(Pulse width modulation: PWM)방식을 사용한다. 제안된 위상검출기 회로는 클럭 반주기만큼의 up/down 펄스폭을 갖는 출력으로 전압제어발진기를 조절하는 펄스수변조(Pulse number modulation: PNM)방식을 사용하여, 전압제어발진기를 미세하게 조절함으로써 지터를 줄일 수 있다. 제안된 위상검출기를 이용한 클럭 및 데이터 복원회로는 1Gbps의 전송률을 갖는 231-1개의 랜덤 데이터를 이용하여 테스트되었고, 지터와 전력소비는 각각 7.36ps와 12mW로 저전력, 적은 지터의 특징을 보였다. 제안된 회로는 0.18um CMOS 공정에서 1.8V 전원으로 설계되었다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
• /
• pp.2180-2183
• /
• 2003

본 논문에서는 광 디스크의 기록 밀도 증가에 따른 신호품질의 열화나 노이즈가 심한 환경에서 DPLL(Digital Phase Locked Loop)의 성능을 개선하기 위한 FD(Frequency Detector)와 PD(Phase Detector) 알고리즘을 제안한다. 제안된 PD 알고리즘은 노이즈에 의해 왜곡되어 RLL 조건을 위배하는 입력신호, 즉 RLL 조건에 의해 결정되는 최소 런 길이보다 주기가 작은 신호에 의해 발생하는 위상오차를 위상오차 보정 시 사용하지 않도록 설계하여 잘못된 정보에 의한 위상오차 보정이 일어나지 않도록 하였다 제안된 FD 알고리즘은 주파수를 추적하기 위해 삽입되는 신호인 Sync 신호의 symmetry 특성을 이용하여 샘플패턴을 검출하도록 하여 기존의 주파수 오차 보정 알고리즘보다 향상된 주파수 추적 성능을 가지도록 하였다.

• Journal of information and communication convergence engineering
• /
• 제9권3호
• /
• pp.305-309
• /
• 2011

This paper proposes a new rotational frequency detector (RFD) for phase-locked loop (PLL) or clock and data recovery (CDR) applications for fast frequency acquisition. The proposed RFD uses the four states finite state machine (FSM) model to accelerate the frequency acquisition time. It is modeled and simulated with MATLAB Simulink. The functionalities of the proposed RFD are examined and the results are compared to those of a conventional RFD. The proposed RFD's frequency acquisition time is four times faster than that of a conventional one. The proposed RFD incorporated with a phase detector (PD) in PLL or CDR is expected to improve the frequency and phase acquisition performance later greatly.

• ETRI Journal
• /
• 제35권2호
• /
• pp.218-225
• /
• 2013

The pull-out frequency of a second-order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull-out frequency for a second-order Type II PLL that employs a sinusoidal characteristic phase detector. The pull-out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제6권4호
• /
• pp.264-269
• /
• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• KIEE International Transactions on Electrophysics and Applications
• /
• 제4C권1호
• /
• pp.1-4
• /
• 2004

This paper presents an investigation of the phase-resolved partial discharge (PD) pattern of PET (Poly Ethylene Telephthalate) films with carbon black particles. The phase-resolved PD pattern and statistical parameter from PET samples according to the number of included semiconductor particles were measured. The measurement system consisted of a conventional PD detector using a digital signal processing technique. The partial discharge patterns of the PET films that include the semiconductor particles were investigated to simulate an actual situation that may exist in the cable. In addition, difference of PD patterns between semiconducting particles in PET films and artificial voids was studied. The relationship between the numbers of semiconductor particles in PET films was discussed through the difference of Ψ-q-n distribution and statistical analysis.