A CMOS 5.4/3.24-Gbps Dual-Rate CDR with Enhanced Quarter-Rate Linear Phase Detector

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.