• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.110-114
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• 1987

A method for synthesizing low-pass elliptic filters in a microstrip configuration is presented. The realization consists of the cascade connection of proper rectangular elements, each one corresponding to four reactive elements of the lumped-constant prototype. This allows an effictive control of parasitics and unwanted reactances. Which results in the possibility of realizing higher order filters with cutoff frequencies UP to X-band. Fifth and seventh order filters were fabricated on allumina substrates.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.645-648
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• 1998

We used a three-dimensional inductance extraction program, Fasthenry for optimal design of the spiral inductors on silicon substrate. The inductance and quality factor of the spiral inductors with various design parameters were calculated so that the optimal parameter value was determined. The spiral inductors then were fabricated using different foundary processes and were measured using the network analyzer and microwave probes. The pad and other parasitics of measurement system were de-embedded using the y-parameter calibration technique. the inductors fabricated using the LG 0.8um process and HP 0.5um process showed the quality factor of 5.8 and 3, respectively. Finally the equivalent circuit farameters of the spiral inductors on silicon substrate were extracted from the measurement data using the matlab.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.67-70
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• 2003

In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on circuits, optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.25-${\mu}m$ process, also including the parasitics derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, except for short chains of blocks or for cases where minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.92-98
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• 1996

parallel bonding wires separaated with a screeing bonding wire are proposed and characterized in order to redue mutual coupling and parasitics of high-speed and high-density device packaging. The mehtod of moments (MoM) with the incorporation of the ohmic loss has been used in a wide range of frequencies. From the calculated results, we have found that the screening bonding wire effectively reduces inductive and capacitive crostalk levels more than 3dB. the parasitic self inductance is also reduced more than 12% by the screening effect. Therefore, for a general VLSi package, the packaging density can be increased more than 30% using the screening bonding wire. This screeing bonding wire and the analysis can be effectively used to reduce crosstalk and increase packaging density of high density devices.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.4
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• pp.483-486
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• 2014

Although flip-chip interconnects have smaller parasitics than bonding wires, they should be carefully designed at 60 GHz. Insertion loss at a flip-chip transition may differ as much as 2 dB depending on design parameters. In this paper we present a comprehensive sensitivity analysis to optimize the flip-chip transition.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.163-167
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• 2003

In this paper, an air-suspension type RF MEMS inductor is fabricated, and an appropriate de-embedding scheme for 3-dimenstional MEMS structure is applied and verified with inductance calculation algorithm. With the presented de-embedding method, parasitics from contanct pads and feeding lines are effectively and accurately de-embedded using open and short calibration procedure, and only spiral and posts can be characterized as a high-Q inductor structure. The validity of the de-embedding method is verified by the comparison of the measured and calculated inductances of two 1.5 and 2.5 turn square spiral inductors. The open-short de-embedded inductance error is below 5% each case in comparison with the calculated value based on H.M. Greenhouse's algorithm.

• Journal of Power Electronics
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• v.9 no.2
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• pp.308-319
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• 2009

An increasing number of power electronic applications require high power density. Therefore, the switching frequency and switching speed have to be raised considerably. However, the very fast switching transients induce a strong voltage and current ringing. In this work, a novel damping concept is introduced where the parasitic wiring inductances are advantageously magnetically coupled with a damping layer for attenuating these unwanted oscillations. The proposed damping layer can be implemented using standard materials and printed circuit board manufacturing processes. The system behavior is analyzed in detail and design guidelines for a damping layer with optimized RC termination network are given. The effectiveness of the introduced layer is determined by layout parasitics which are calculated by application of the Partial Element Equivalent Circuit (PEEC) simulation method. Finally, simulations and measurements on a laboratory prototype demonstrate the good performance of the proposed damping approach.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05b
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• pp.27-30
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• 2003

In this paper, the new dual trench gate Emitter Switched Thyristor (DTG-EST) is proposed for improving snap-back effect which leads to a lot of serious problems of device applications. And the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and $35A/cm^2$, respectively. But the proposed DTG-EST exhibits snap-back with the anode voltage and current density 0.96V and $100A/cm^2$, respectively.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.617-618
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• 2006

A CMOS quadrature Up-converter for a direct-conversion receiver of 5.15-5.825GHz wireless LAN is described. The Up-converter consists of two sub-harmonic mixers, for I and Q channels, and an LO generation network. In order to decrease the number of inductor, I and Q path are merged. The simulation results including all the parasitics show -17.3dB conversion gain at center and -8 dBv oIP3 while consuming 22.968mW under 1.8V supply. The quadrature Up-converter is under fabrication with the other transmitter blocks in a $0.18{\mu}m$ CMOS technology.

• Carbon letters
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• v.13 no.1
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• pp.17-22
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• 2012

Currently, graphene is a topic of very active research in fields from science to potential applications. For various radio-frequency (RF) circuit applications including low-noise amplifiers, the unique ambipolar nature of graphene field-effect transistors can be utilized for high-performance frequency multipliers, mixers and high-speed radiometers. Potential integration of graphene on Silicon substrates with complementary metal-oxide-semiconductor compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene metal-oxide-semiconductor field-effect transistors to minimize parasitics and improve gate modulation efficiency in the channel. In this paper, we highlight recent progress in graphene materials, devices, and circuits for RF applications. For passive RF applications, we show its transparent electromagnetic shielding in Ku-band and transparent antenna, where its success depends on quality of materials. We also attempt to discuss future applications and challenges of graphene.