• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.3
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• pp.339-353
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• 2014

A straightforward method for optimal determining of a high frequency inductor's parasitic capacitance is presented. The proposed estimation method is based on measuring the inductor's impedance samples over a limited frequency range bordering on the resonance point considering k-dB deviation from the maximum impedance. An optimized solution to k could be obtained by minimizing the root mean squared error between the measured and the estimated impedance values. The model used to provide the estimations is a parallel RLC circuit valid at resonance frequency which will be transferred to the real model considering the mentioned interval of frequencies. A straightforward algorithm is suggested and programmed using MATLAB which does not require a wide knowledge of design parameters and could be implemented using a spectrum analyzer. The inputs are the measured impedance samples as a function of frequency along with the diameter of the conductors. The suggested algorithm practically provides the estimated parameters of a real inductance model at different frequencies, with or without design information. The suggested work is different from designing a high frequency inductor; it is rather concentration of determining the parameters of an available real inductor that could be easily done by a recipe provided to a technician.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.42-44
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• 2007

The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.250-256
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• 2007

We analyzed the effect of a pixel and all the inter-electrode capacitances in a unit pixel of TFT-LCDs on the gray scale capability. The pixel and all the inter-electrode parasitic capacitances were obtained from the tree dimensional profiles of potential distribution and molecular director considering lateral fields generated at the edge of the pixel. To obtain the RMS and kickback voltages of the pixel, we constructed an equivalent circuit of the panel containing all the parasitic capacitances. The calculation was performed though H-SPICE. As results, we confirmed that the pixel becomes smaller, the effect of parasitic capacitances on the gray scale capability becomes larger.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.249-252
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• 2003

This paper propose an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog to comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an exective isolation strategy for removing noise and signal coupling of each sensor pixel. The 128$\times$144 pixel fingerprint sensor circuit was designed and simulated, and the layout was performed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.274-280
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• 2007

This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance ($C_{IN}$) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic $C_{IN}$ affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.3
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• pp.116-122
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• 2003

This paper proposes an efficient method for computing the 3-dimensional capacitance of complex structures. The proposed method Is based on Finite Element Method(FEM) and expands the conventional FEM by adopting variable division. This method improves the extraction efficiency 50 times when compared to the conventional FEM with equal division. The proposed method can be used efficiently to extract electrical parameters of on/off-chip interconnects in VLSI systems.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1093-1096
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• 2008

The circuit simulation has been done on the current-programmed AMOLED and shows that the circuit which behaves as a negative capacitance can reduce the effect of parasitic capacitance fixed on the data-line and can accelerate the current programming speed as high as that required in Full HD AMOLED.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.25-31
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• 2016

Parasitic capacitance and resistance of FinFET transistors are the important components that determine the frequency performance of the circuit. Therefore, the researchers in our group developed more accurate parasitic capacitance and resistance for FinFETs than BSIM-CMG. To verify the RF performance, proposed model was applied to design an LNA that has $S_{21}$ more than 10dB and center frequency more than 60GHz using HSPICE. To verify the accuracy of the proposed model, mixed-mode capability of 3D TCAD simulator Sentaurus was used. $S_{21}$ of LNA was chosen as a reference to estimate the error. $S_{21}$ of proposed model showed 87.5% accuracy compared to that of Sentaurus in 10GHz~100GHz frequency range. The $S_{21}$ accuracy of BSIM-CMG model was 56.5%, so by using the proposed model, the accuracy of the circuit simulator improved by 31%. This results validates the accuracy of the proposed model in RF domain and show that the accuracies of the parasitic capacitance and resistance are critical in accurately predicting the LNA performance.

• Proceedings of the Optical Society of Korea Conference
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• 2003.02a
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• pp.300-301
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• 2003

As the demand for high frequency(bandwidth) optical module is increased, there is a need for fabricating silicon optical bench(SiOB) with low parasitic impedance. In this paper, we discuss multi-layer structure method for manufacturing SiOB with low capacitance. This structure method decreases the capacitance between the conductive patterns for about 94∼97％ compared to the conventional structure without raising the resistivity of silicon, or increasing the thickness of the dielectric film.