• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.8
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• pp.799-805
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• 2004

Two dimensional MEDICI simulator is used to study the characteristics of latch-up current of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics, latch-up current density, ON-voltage drop and electrical property with the variations of p-base impurity concentrations. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have the better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer p-base structure under the floating $N^+$ emitter indicates to have the better characteristics of latch-up current and breakover voltage.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.131-139
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• 1996

Inthis apper wa analyzed the channel-hot-electron programming characteristics of the single-poly EEPROM with different control gate and drain structures. The single-poly EEPROM uses the p$^{+}$/n$^{+}$-diffusion in the n-well as a control gate instead of the second poly-silicon. The program and erase characteristics of the single-poly EEPROM were verified using the two-dimensional device simulator, MEDICI. The single-poly EEPROM was fabricated using 0.8$\mu$m ASIC CMOS process, and its CHE programming characteristics were measured using HP4155 parameteric analyzer and HP8110 pulse gnerator. Especially we investigated the CHE programming characteristics of the single-poly EEPROM with the p$^{+}$-diffusion or n$^{+}$-diffusion in the n-well as a control gate and the LDD or single-drain structure. The single-poly EEPROM with p$^{+}$-diffusion in the n-well as a control gate and single-drain structure was programmed to about VT$\thickapprox$5V with VDS=6V, VCG=12V(1ms pulse width).th).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.605-610
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• 2010

The devices based on electrically erasable programmable read-only memory (EEPROM) structure are proposed for the detection of external electric charges. A large size charge contact window (CCW) extended from the floating gate is employed to immobilize external charges, and a control gate with stacked metal-insulator-metal (MIM) capacitor is adapted for a standard single polysilicon CMOS process. When positive voltage is applied to the capacitor of CCW of an n-channel EEPROM, the drain current increases due to the negative shift of its threshold voltage. Also when a pre-charged external capacitor is directly connected to the floating gate metal of CCW, the positive charges of the external capacitor make the drain current increase for n-channel, whereas the negative charges cause it to decrease. For an p-channel, however, the opposite behaviors are observed by the external voltage and charges. With the attachment of external charges to the CCW of EEPROM inverter, the characteristic inverter voltage behavior shifts from the reference curve dependent on external charge polarity. Therefore, we have demonstrated that the EEPROM inverter is capable of detecting external immobilized charges on the floating gate. and these devices are applicable to sensing the pH's or biomolecular reactions.

• Journal of the Semiconductor & Display Technology
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• v.12 no.4
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• pp.21-25
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• 2013

This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to 4 V in the previous work. This is because the surface effect at the drain side decreases the channel current and the impact ionization in the channel at high drain voltage. In order to increase the breakdown voltage at the same asymmetric gate-recess structure, the InGaAs channel structure is replaced with the InGaAs/InP composite channel in the simulation. The simulation results with InGaAs/InP channel show that the breakdown voltage increases to 6V in the MHEMT as the current decreases. In this paper, the simulation results for the InGaAs/InP channel are shown and analyzed for the InGaAs/InP composite channel in the MHEMT.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.491-491
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• 2011

Transparent and flexible electronic devices that are light-weight, unbreakable, low power consumption, optically transparent, and mechanical flexible possibly have great potential in new applications of digital gadgets. Potential applications include transparent displays, heads-up display, sensor, and artificial skin. Recent reports on transparent and flexible field-effect transistors (tf-FETs) have focused on improving mechanical properties, optical transmittance, and performances. Most of tf-FET devices were fabricated with transparent oxide semiconductors which mechanical flexibility is limited. And, there have been no reports of transparent and flexible all-organic tf-FETs fabricated with organic semiconductor channel, gate dielectric, gate electrode, source/drain electrode, and encapsulation for sensor applications. We present the first demonstration of transparent, flexible all-organic sensor based on multifunctional organic FETs with organic semiconductor channel, gate dielectric, and electrodes having a capability of sensing infrared (IR) radiation and mechanical strain. The key component of our device design is to integrate the poly(vinylidene fluoride-triflouroethylene) (P(VDF-TrFE) co-polymer directly into transparent and flexible OFETs as a multi-functional dielectric layer, which has both piezoelectric and pyroelectric properties. The P(VDF-TrFE) co-polumer gate dielectric has a high sensitivity to the wavelength regime over 800 nm. In particular, wavelength variations of P(VDF-TrFE) molecules coincide with wavelength range of IR radiation from human body (7000 nm ~14000 nm) so that the devices are highly sensitive with IR radiation of human body. Devices were examined by measuring IR light response at different powers. After that, we continued to measure IR response under various bending radius. AC (alternating current) gate biasing method was used to separate the response of direct pyroelectric gate dielectric and other electrical parameters such as mobility, capacitance, and contact resistance. Experiment results demonstrate that the tf-OTFT with high sensitivity to IR radiation can be applied for IR sensors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.145-152
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• 2003

Electrical gate and drain characteristics of double heterostructure InAlAs/InGaAs pseudomorphic HEMTs have been investigated under sub-bandgap photonic excitation ($hv). Drain $(V_{DS})-,{\;}gate($V_{DS})-$, and optical power($P_{opt}$)-dependent variation of the abnormal gate leakage current and associated physical mechanisms in the PHEMTs have been characterized. Peak gate voltage ($V_{GS,P}$) and the onset voltage for the impact ionization ($V_{GS.II}$) have been extracted and empirical model for their dependence on the $V_{DS}$ and $P_{opt} have been proposed. Anomalous gate and drain current, both under dark and under sub-bandgap photonic excitation, have been modeled as a parallel connection of high performance PHEMT with a poor satellite FET as a parasitic channel. Sub-bandgap photonic characterization, as a function of the optical power with $h\nu=0.799eV$, has been comparatively combined with those under dark condition for characterizing the bell-shaped negative humps in the gate current and subthreshold drain leakage under a large drain bias.

• Journal of the Korean Vacuum Society
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• v.22 no.6
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• pp.335-340
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• 2013

This paper is for the simulation design to enhance the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess and channel structures has been simulated and analyzed for the breakdown of the MHEMT devices. The fully removed recess structure at the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to almost 4 V as the saturation current at gate voltage of 0 V is reduced from 90 mA to 60 mA at drain voltage of 2 V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier and the $Si_3N_4$ passivation layers deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer and thus the impact ionization in the channel become smaller. In addition, the replaced InGaAs/InP composite channel with the same thickness in the same asymmetrically recessed structure increases the breakdown voltage to 5 V due to the smaller impact ionization and mobility of the InP layer at high drain voltage.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.708-714
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• 1995

We have discussed the buried-channel(BC) behavior through the subthreshold characteristics of submicron PMOSFET device fabricated with twin well CMOS process. In this paper, we have guessed the initial conditions of ion implantation using process simulation, obtained the subthreshold characteristics as a function of process parameter variation such as threshold adjusting ion implant dose($D_c$), channel length(L), gate oxide thickness($T_ox$) and junction depth of source/drain($X_j$) using device simulation. The buried channel behavior with these process prarameter variation were showed apparent difference. Also, the fabricated pMOSFET device having different channel length represented good S.S value and low leakage current with increasing drain voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.177-184
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• 2014

In chemical vapor deposition(CVD) tungsten silicide(WSix) dual poly gate(DPG) scheme, we observed the fluorine effects on gate oxide using the electrical and physical measurements. It is found that in fluorine-rich WSix NMOS transistors, the gate thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In PMOS transistors, it is observed that boron of background dopoing in $p^+$ poly retards fluorine diffusion into the gate oxide. Thus, it is suppressed the fluorine effects on gate oxide thickness with the channel length dependency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.489-492
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• 1999

The effects of alternate bias stress on p-channel poly-Si TPT's has been systematically investigated. It has been shown that the application of alternate bias stress affects device degradation for the negative bias stress as well as device improvement for the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ under bias stress.