• The Journal of the Acoustical Society of Korea
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• v.41 no.2
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• pp.184-191
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• 2022

Underwater acoustic wave in shallow water is propagated through multipath that has a large delay spread causing Inter-Symbol Interference (ISI) and these characteristics deteriorate the performance in the communication system. In order to analyze the communication performance and investigate the correlation with multipath delay spread in a reverberant environment, an underwater acoustic communication experiment using Binary Phase-Shift Keying (BPSK) signals with symbol rates from 100 sym/s to 8000 sym/s was conducted in a 5 × 5 × 5 m³ water tank. The acoustic channels in a well-controlled tank environment had the characteristics of dense multipath delay spread due to multiple reflections from the interfaces and walls within the tank and showed the maximum excess delay of 40 ms or less, and the Root Mean Squared (RMS) delay spread of 8 ms or less. In this paper, the performances of Bit Error Rate (BER) and output Signal-to-Noise Ratio (SNR) were analyzed using four types of communication demodulation techniques. And the parameter, Symbol interval to Delay spread Ratio in reverberant environment (SDR_rev), which is the ratio of symbol interval to RMS delay spread in the reverberant environment is defined. Finally, the SDR_rev was compared to the BER and the output SNR. The results present the reference symbol rate in which high communication performance can be guaranteed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.169-175
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• 2020

This paper studied the SET situation in VLSI because the electronic devices exposed to SET can indicate irregular operation and output errors. The SET environment was established using the exponential static wave (iexp) in the fold-cascode comparator. The comparator was experimented with how it affected it by the SET. In a folded comparator that did not enter the SET situation, the propagation delay was measured at 0.26㎲ and the gain was 0.649. The MOSFET close to the output stage was measured sensitively in the folded comparator that entered the SET situation. And propagation delay was calculated from 0.36 to 0.37㎲ and the gain was 0.649. The mid-position MOSFET was calculated from 0.28 to 0.30㎲ and the gain was 0.649. The MOSFET, which is farthest from the output stage from the folded comparator, was calculated with the propagation delay between 0.25 and 0.26㎲ and the gain of 0.649. In SET situations, the MOSFET close to the output portion of the folded comparator was sensitive. And at the MOSFET far from the output, the same results were obtained as a normal folded comparator without the SET input.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.3
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• pp.1147-1152
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• 2012

In this paper, it is key issue about analysis of characteristics processing of digital random output stream of hardware random number generator, which is applied in medical area. The output stream of random number generator based on hardware binary random number is effected from factors such as delay, jitter, temperature, and so on. In this paper, it presents about major factor, which effects hardware output random number stream, and the randomness of output stream data, which are combined output stream and postprocessing data such as encryption algorithm, encoding algorithm, is analyzed. the analyzed results are evaluated by major test items of randomness.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7A
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• pp.762-769
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• 2007

Adaptive MIMO-OFDM (Orthogonal Frequency Division Multiplexing) system adaptively changes modulation scheme depending on feedback channel state information (CSI). The CSI feedback channel which is the reverse link channel has multiple symbol delays including propagation delay, processing delay, frame delay, etc. The unreliable CSI due to feedback delay degrades adaptive modulation system performance. This paper compares the MSE and data capacity with respect to delay and channel signal to noise ratio for the two multi-step channel prediction schemes, CTSBP and BTSBP, such that robust adaptive SISO-OFDM/MIMO-OFDM is designed over severe mobile multipath channel conditions. This paper presents an interpolation method to reduce feedback overhead for adaptive MIMO-OFDM and shows MSE with respect to interpolation interval.

• Journal of Positioning, Navigation, and Timing
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• v.11 no.2
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• pp.71-81
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• 2022

In order for electro-optical tracking system (EOTS) to have accurate target coordinate, accurate navigation results are required. If an integrated navigation system is configured using an inertial measurement unit (IMU) of EOTS and the vehicle's navigation results, navigation results with high rate can be obtained. Due to the time-delay of the navigation results of the vehicle in the EOTS and scale factor errors of the EOTS IMU in high-speed and high dynamic operation of the vehicle, it is much more difficult to have accurate navigation results. In this paper, an integrated navigation system of EOTS which compensates time-delay and scale factor error is proposed. The proposed integrated navigation system consists of vehicle's navigation system which provides time-delayed navigation results, an EOTS IMU, an inertial navigation system (INS), an augmented Kalman filter and integration Kalman filter. The augmented Kalman filter outputs navigation results, in which the time-delay of the vehicle's navigation results is compensated. The integration Kalman filter estimates position, velocity, attitude error of the EOTS INS and accelerometer bias, accelerometer scale factor error, gyro bias and gyro scale factor error from the difference between the output of the augmented Kalman filter and the navigation result of the EOTS INS. In order to check performance of the proposed integrated navigation system, simulations for output data of a measurement generator and land vehicle experiments were performed. The performance evaluation results show that the proposed integrated navigation system provides more accurate navigation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1713-1719
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• 2022

As the noise canceler with a small processing delay increases the sampling frequency, a better-quality output can be obtained. For a single buffer, processing delay occurs because it is impossible to write new data while the processor is processing the data. When synthesizing with anti-noise and output signal, this processing delay creates additional buffering overhead to match the phase. In this paper, we propose an accelerator structure that minimizes processing delay and increases processing speed by alternately performing read and write operations using the Symmetric Even-Odd-buffer. In addition, we compare the structural differences between the two methods of noise cancellation (Fast Fourier Transform noise cancellation and adaptive Least Mean Square algorithm). As a result, using an Symmetric Even-Odd-buffer the processing delay was reduced by 29.2% compared to a single buffer. The proposed Symmetric Even-Odd-buffer structure has the advantage that it can be applied to various canceling algorithms.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.3
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• pp.324-329
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• 2005

In this paper, a robust $H\infty$ stabilization problem to a uncertain discrete-time nonlinear systems with time-delay via fuzzy static output feedback is investigated. The Takagj-Sugeno (T-S) fuzzy model is employed to represent an uncertain nonlinear system with time-delayed state. Then, the parallel distributed compensation technique is used for designing of the robust fuzzy controller. Using a single Lyapunov function, the globally asymptotic stability and disturbance attenuation of the closed-loop fuzzy control system are discussed. Sufficient conditions for the existence of robust $H\infty$ controllers are given in terms of linear matrix inequalities via similarity transform and congruence transform technique. We have shown the effectiveness and feasibility of the proposed method through the simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.17-22
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• 2012

A novel Clock Generator with jitter suppressed delay-locked loop (DLL) has been proposed to generate highly accurate output signals. The proposed Clock Generator has a VCDL which can suppress its jitter by generating control signals proportional to phase differences among delay stages. It has been designed to generate 1GHz output at 100MHz input with 1.8V $0.18{\mu}m$ CMOS process. The simulation result demonstrates a 3.24ps of peak-to-peak jitter.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.11
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• pp.1564-1570
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• 2015

This paper intends to suggest a sensing circuit of PWM voltage for a motor emulator operated in the inverter. In the emulation of the motor using a power converter, it is necessary to measure instantaneous voltage at the PWM voltage loaded from the inverter. Using a filter can generate instantaneous voltage, while it is difficult to follow the rapidly changing inverter voltage caused by the propagation delay and signal attenuation. The method of measuring the duty of PWM using FPGA can generate output voltage from the one-cycle delay of PWM, while the cost of hardware is increasing in order to acquire high precision. This paper suggests a PWM voltage sensing circuit using the analogue system that shows high precision, one-cycle delay of PWM and low-cost hardware. The PWM voltage sensing circuit works in the process of integrating input voltage for valid time by comparing levels of three-phase PWM input voltage, and produce the output value integrated at zero vector. As a result of PSIM simulation and the experiment with the produced hardware, it was verified that the suggested circuit in this paper is valid.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.137-144
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• 2013

A delay-locked loop (DLL) that generates a 32-phase clock with the operating frequency of 125 MHz is introduced. The proposed DLL uses a delay line of $4{\times}8$ matrix architecture to improve a differential non-linearity (DNL) of the delay line. Furthermore, a integral non-linearity (INL) of the proposed DLL is improved by calibrating phases of clocks that is supplied to four points of an input stage of the $4{\times}8$ matrix delay line. The proposed DLL is fabricated by using $0.11-{\mu}m$ CMOS process with a 1.2 V supply. The measured operating frequency range of the implemented DLL is 40 MHz to 280 MHz. At the operating frequency of 125MHz, the measurement results shows that the DNL and INL are +0.14/-0.496 LSB and +0.46/-0.404 LSB, respectively. The measured peak-to-peak jitter of the output clock is 30 ps when the peak-to-peak jitter of the input clock is 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW, respectively.