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http://dx.doi.org/10.6109/jkiice.2022.26.11.1713

Lightweight FPGA Implementation of Symmetric Buffer-based Active Noise Canceller with On-Chip Convolution Acceleration Units  

Park, Seunghyun (School of Electronics Engineering, Kyungpook National University)
Park, Daejin (School of Electronics Engineering, Kyungpook National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.26, no.11, 2022 , pp. 1713-1719 More about this Journal
Abstract
As the noise canceler with a small processing delay increases the sampling frequency, a better-quality output can be obtained. For a single buffer, processing delay occurs because it is impossible to write new data while the processor is processing the data. When synthesizing with anti-noise and output signal, this processing delay creates additional buffering overhead to match the phase. In this paper, we propose an accelerator structure that minimizes processing delay and increases processing speed by alternately performing read and write operations using the Symmetric Even-Odd-buffer. In addition, we compare the structural differences between the two methods of noise cancellation (Fast Fourier Transform noise cancellation and adaptive Least Mean Square algorithm). As a result, using an Symmetric Even-Odd-buffer the processing delay was reduced by 29.2% compared to a single buffer. The proposed Symmetric Even-Odd-buffer structure has the advantage that it can be applied to various canceling algorithms.
Keywords
Noise cancellation; Symmetric Even-Odd-buffer; FFT; Adaptive LMS algorithm; FPGA;
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