Journal of the Korea Academia-Industrial cooperation Society (한국산학기술학회논문지)

The Korea Academia-Industrial cooperation Society (한국산학기술학회)
권호 표지
DOI QR코드

DOI QR Code

Analysis of Output Stream Characteristics Processing in Digital Hardware Random Number Generator

디지털 하드웨어 난수 발생기에서 출력열 특성 처리 분석

  • Hong, Jin-Keun (Division of Information Communication, Baekseok University)
  • 홍진근 (백석대학교 정보통신학부)
  • Received : 2011.12.21
  • Accepted : 2012.03.08
  • Published : 2012.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, it is key issue about analysis of characteristics processing of digital random output stream of hardware random number generator, which is applied in medical area. The output stream of random number generator based on hardware binary random number is effected from factors such as delay, jitter, temperature, and so on. In this paper, it presents about major factor, which effects hardware output random number stream, and the randomness of output stream data, which are combined output stream and postprocessing data such as encryption algorithm, encoding algorithm, is analyzed. the analyzed results are evaluated by major test items of randomness.

본 논문은 의학 분야에서 사용되는 하드웨어 발생기 디지털 난수 출력열의 특성 처리 분석을 주요 이슈로 한다. 하드웨어 이진 난수를 기반으로 하는 난수발생기의 출력열은 지연, 지터, 온도 등의 요소로부터 영향을 받는다. 본 논문에서는 하드웨어 출력 난수열에 영향을 주는 주요 요소에 대해 살펴보고, 출력열과 암호알고리즘, 부호알고리즘이 결합된 출력열의 난수성을 분석하였다. 분석된 결과는 난수성 주요 검증 항목에 의해 평가되었다.

Keywords

References

  1. P. Lacharme, "Post-processing functions for a biased physical random number generator,"in Fast Software Encryption workshop - FSE 2008.
  2. E. Barker and J. Kelsey, "Nist special publication 800-90: Recommendation for random number generation using deterministic random bit generators,"National Institute of Standards and Technology (NIST), Computer Security Division Information Technology Laboratory, March 2007.
  3. M. Dichtl, "Bad and good ways of post-processing biased physical random numbers,"in Fast Software Encryption workshop - FSE 2007.
  4. F. Pareschi, G. Setti, and R. Rovatti, "A fast chaos-based true random number generator for cryptographic applications,"in Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European, September 2006, pp. 130-133.
  5. M. Drutarovsky and P. Galajda, "A robust chaos-based true random number generator embedded in recongurable switched-capacitor hardware," in Radio elektronika, 2007. 17th International Conference, April, pp. 1-6.
  6. B. Valtchanov, A. Aubert, F. Bernard, and V. Fischer, "Modeling and observing the jitter in ring oscillators implemented in fpgas,"in The 11-th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Bratislava, April 2008, pp. 158-163.
  7. V. Fischer, F. Bernard, N. Bochard, and M. Varchola, "Enhancing security of ring oscillator based rng implemented in fpga," in Field-Programable Logic and Applications (FPL), September 2008, pp. 245-250.
  8. M. Varchola, "Design and evaluation of optimized fpga ip-cores for cryptography," in Computer Architectures & Diagnostics (Pocitacove Architektury & Diagnostika - PAD), September 2008, pp. 113-118.
  9. V. Fischer and M. Drutarovsky, "rue random number generator embedded in reconfigurable hardware," in CHES '2: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems. London, UK: Springer-Verlag, 2003, pp. 415-30.
  10. D. Schellekens, B. Preneel, and I. Verbauwhede, "pga vendor agnostic true random number generator," in Field Programmable Logic and Applications, 2006. FPL '6, 2006, pp. 1-6.