• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.3
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• pp.126-132
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• 2011

A conventional LDO(Low Dropout Regulator) uses one OPAMP and one signal path. This means that OPAMP's DC Gain and Bandwidth can't optimize simultaneously within usable power. This also appears that regulation property and settling time of LDO can't improve at the same time. Based on this idea, a proposed LDO uses two OPAMP and has two signal path. To improve regulation property, OPAMP where is used in the path which qualities DC gain on a large scale, bandwidth designed narrowly. To improve settling time, OPAMP where is used in the path which qualities DC gain small, bandwidth designed widely. A designed LDO used 0.5um 1P2M process and provided 200mA of output current. A line regulation and load regulation is 12.6mV/V, 0.25mV/mA, respectively. And measured settling time is 1.5us in 5V supply voltage.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.522-525
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• 1998

본 논문에서는 아날로그 증폭기의 특성 개선을 통해 아날로그 신호처리 시스템의 동작속도를 향상시키기 위해서 2단 연산증폭기 (two-stage opamp:TSO)의 주파수 응답 특성과 이득을 개선하기 위한 회로를 설계하고 시물레이션을 통해서 설계된 회로의 우수성을 증명하였다.

• Journal of Sensor Science and Technology
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• v.26 no.1
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• pp.60-65
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• 2017

This paper describes the low noise and low power IC using the opamp sharing technique for the capacitive micro-sensor sensing platform. The proposed IC reduces noise using correlated double sampling (CDS) and reduces power consumption using the opamp sharing technique. The IC is designed to be fully programmable, and can be digitally controlled by serial peripheral interface (SPI). The power consumption and the integrated input referred noise are 1.02 mW from a 3.3 V supply voltage and $0.164aF_{RMS}$ with a bandwidth of 400 Hz. The capacitive sensitivity, the input-output linearity and the figure of merits (FoM) are 2.5 mV/fF, 2.46 %FSO, and 8.4, respectively.

• Transactions on Electrical and Electronic Materials
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• v.15 no.3
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• pp.149-154
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• 2014

A new CMOS analog design methodology using an independently optimized self-cascode (SC) is proposed. This idea is based on the concept of the dual-workfunction-gate MOSFETs, which are equivalent to SC structures. The channel length of the source-side MOSFET is optimized, to give higher transconductance ($g_m$) and output resistance ($r_{out}$). The highest $g_m$ and $r_{out}$ of the SC structures are obtained by independently optimizing the channel length ratio of the SC MOSFETs, which is a critical design parameter. An operational amplifier (OPAMP) with the proposed design methodology using a standard digital $0.18-{\mu}m$ CMOS technology was designed and fabricated, to provide better performance. Independently $g_m$ and $r_{out}$ optimized SC MOSFETs were used in the differential input and output stages, respectively. The measured DC gain of the fabricated OPAMP with the proposed design methodology was approximately 18 dB higher, than that of the conventional OPAMP.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.26-32
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• 2017

This paper presents a low power and high resolution incremental delta-sigma ADC that utilizes a passive integrator instead of an opamp-based active integrator. Opamp is a power-hungry block that involves tight design tradeoffs. To avoid the use of active integrator, the s-domain characteristic of an active integrator is first analyzed. Based on the analysis, an active integrator with low gain design is proposed as an alternative design method. To save power even more aggressively, a passive integrator with no static current is proposed. A 1st order single-bit incremental delta-sigma ADC using the proposed passive integrator is implemented in a 65nm CMOS process. Transistor-level simulation shows that the ADC consumes only 0.6uW under 1.2V supply while achieving SNDR of 71dB with 22kHz bandwidth. The estimated total power consumption including digital filter is 6.25uW, and resulting power efficiency is on a par with state-of-the-art A/D converters.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.416-424
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• 2014

This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.868-871
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• 2005

In this article, presents an analog multiplier using a general-purpose operational amplifier (opamp). The realization method is based on the quarter-square technique, which utilize the square-law characteristic of the class AB output stage of the opamp. The experimental results verifying the proposed multiplier performances are also included. The linearity error and the total harmonic distortion is about 0.8% and 1.6%, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.726-729
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• 2013

In this paper, low power and high slew rate CMOS rail to rail input/output opamp applicable for ouput buffer amp, in LCD source driver IC, is proposed. Proposed op-amp, is realized the characteristics of low power consumption and high slew rate adding the newly designed control stage of class-B to the conventional output stage of class-AB. From the simulation results, we know that the proposed opamp buffer can drive a 1000pF capacitive load with a 6.5V/us slew-rate, while drawing only the the power consumption of 1.19mW from 3.3V power supply.

• Journal of IKEEE
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• v.18 no.2
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• pp.263-271
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• 2014

This paper presents design of the second-order sigma-delta modulator for converting voltage and temperature signals to digital ones in Battery Management IC (BMIC) for mobile applications. The second-order single-loop switched-capacitor sigma-delta modulator with 1-bit quantization in 0.13-um CMOS technology is proposed. The proposed modulator is designed using switched-opamp technique for saving power consumption. With an oversampling ratio of 256 and clock frequency of 256kHz, the modulator achieves a measured 83-dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 81.7dB. Power dissipation is about 0.66 mW at 3.3 V power supply and the occupied core area is $0.425mm^2$.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.2
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• pp.81-86
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• 2006

In this paper, a new process detection circuit is proposed. The proposed process detection circuit compares a long channel MOS transistor (L > 0.4um) to a short channel MOS transistor which uses lowest feature size of the process. The circuit generates the differential current proportional to the deviation of carrier mobilities according to the process variation. This method keep the two transistor's drain voltage same by implementing the feedback using a high gain OPAMP. This paper also shows the new design of the simple high gam self-biased rail-to-rail OPAMP using a proposed self-biased super MOS composite circuit. The gain of designed OPAMP is measured over 100dB with $0.2{\sim}1.6V$ wide range CMR in single stage. Finally, the proposed process detection circuit is applied to a differential VCO and the VCO showed that the proposed process detection circuit compensates the process corners successfully and ensures the wide rage operation.