• 제목/요약/키워드: off current

검색결과 2,272건 처리시간 0.029초

저온 제작 다결정 실리콘 박막 트랜지스터의 off-current메카니즘에 관한 연구 (A study on the off-current mechanism of poly-Si thin film transistors fabricated at low temperature)

  • 진교원;김진;이진민;김동진;조봉희;김영호
    • E2M - 전기 전자와 첨단 소재
    • /
    • 제9권10호
    • /
    • pp.1001-1007
    • /
    • 1996
  • The conduction mechanisms of the off-current in low temperature (.leq. >$600^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT'S) have been systematically studied. Especially, the temperature and bias dependence of the off-current between hydrogenated and nonhydrogenated poly-Si TFT's were investigated and compared. The off-current of nonhydrogenated poly-Si TF's is because of a resistive current at low gate and drain voltage, thermally activated current at high gate and low drain voltage, and Poole-Frenkel emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation it has shown that the off -current mechanism is caused mainly by thermal activation and that the field-induced current component is suppressed.

  • PDF

10 nm 이하 무접합 원통형 MOSFET의 온-오프전압△Von-off에 대한 분석 (Analysis of On-Off Voltage △Von-off in Sub-10 nm Junctionless Cylindrical Surrounding Gate MOSFET)

  • 정학기
    • 전기전자학회논문지
    • /
    • 제23권1호
    • /
    • pp.29-34
    • /
    • 2019
  • 본 논문에서는 10 nm 이하 무접합 원통형 MOSFET의 온-오프 전압 ${\Delta}V_{on-off}$에 대하여 고찰하였다. 문턱전압이하 전류가 $10^{-7}A$일 때 게이트 전압을 온 전압, $10^{-12}A$일 때 게이트 전압을 오프 전압으로 정의하고 그 차를 구하였다. 10 nm 이하에서는 터널링 전류를 무시할 수 없기 때문에 터널링 전류의 유무에 따라 ${\Delta}V_{on-off}$의 변화를 관찰하였다. 이를 위하여 포아송방정식을 이용하여 채널 내 전위분포를 구하였으며 WKB 근사를 이용하여 터널링 전류를 구하였다. 결과적으로 10 nm 이하 JLCSG MOSFET에서 터널링 전류에 기인하여 ${\Delta}V_{on-off}$가 증가하는 것을 알 수 있었다. 특히 8 nm 이하의 채널길이에서 급격히 증가하였으며 채널 반지름과 산화막 두께가 증가할수록 ${\Delta}V_{on-off}$는 증가하는 것을 알 수 있었다.

저온제작 Poly-Si TFT′s의 누설전류 (Leakage Current Low-Temperature Processed Poly-Si TFT′s)

  • 진교원;이진민;김동진;김영호
    • 한국전기전자재료학회:학술대회논문집
    • /
    • 한국전기전자재료학회 1996년도 춘계학술대회 논문집
    • /
    • pp.90-93
    • /
    • 1996
  • The conduction mechanisms of the off-current in low temperature ($\leq$600$^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT's) has been systematically studied. Especially, the temperature and bias dependence of the off-current between unpassivated and passivated poly-Si TFT's was investigated and compared. The off-current of unpassivated poly-Si TFT's is due to a resistive current at low gate and drain voltage, thermal emission current at high gate, low drain voltage, and field enhanced thermal emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation, it was observed that the off-currents were remarkably reduced by plasma-hydrogenation. It was also observed that the off-currents of the passivated poly-Si TFT's are more critically dependent on temperature rather than electric field.

  • PDF

Active Controlled Primary Current Cutting-Off ZVZCS PWM Three-Level DC-DC Converter

  • Shi, Yong
    • Journal of Power Electronics
    • /
    • 제18권2호
    • /
    • pp.375-382
    • /
    • 2018
  • A novel active controlled primary current cutting-off zero-voltage and zero-current switching (ZVZCS) PWM three-level dc-dc converter (TLC) is proposed in this paper. The proposed converter has some attractive advantages. The OFF voltage on the primary switches is only Vin/2 due to the series connected structure. The leading-leg switches can obtain zero-voltage switching (ZVS), and the lagging-leg switches can achieve zero-current switching (ZCS) in a wide load range. Two MOSFETs, referred to as cutting-off MOSFETs, with an ultra-low on-state resistance are used as active controlled primary current cutting-off components, and the added conduction loss can be neglected. The added MOSFETs are switched ON and OFF with ZCS that is irrelevant to the load current. Thus, the auxiliary switching loss can be significantly minimized. In addition, these MOSFETs are not series connected in the circuit loop of the dc input bus bar and the primary switches, which results in a low parasitic inductance. The operation principle and some relevant analyses are provided, and a 6-kW laboratory prototype is built to verify the proposed converter.

비대칭 이중게이트 MOSFET의 차단전류에 대한 전도중심 의존성 분석 (Analysis of Conduction-Path Dependent Off-Current for Asymmetric Double Gate MOSFET)

  • 정학기
    • 한국정보통신학회논문지
    • /
    • 제19권3호
    • /
    • pp.575-580
    • /
    • 2015
  • 비대칭 이중게이트(double gate; DG) MOSFET는 단채널 효과를 감소시킬 수 있는 새로운 구조의 트랜지스터이다. 본 연구에서는 비대칭 DGMOSFET의 전도중심에 따른 차단전류를 분석하고자 한다. 전도중심은 채널 내 캐리어의 이동이 발생하는 상단게이트에서의 평균거리로써 상하단 게이트 산화막 두께를 달리 제작할 수 있는 비대칭 DGMOSFET에서 산화막 두께에 따라 변화하는 요소이며 상단 게이트 전압에 따른 차단전류에 영향을 미치고 있다. 전도중심을 구하고 이를 이용하여 상단 게이트 전압에 따른 차단전류를 계산함으로써 전도중심이 차단전류에 미치는 영향을 산화막 두께 및 채널길이 등을 파라미터로 분석할 것이다. 차단전류를 구하기 위하여 포아송방정식으로부터 급수 형태의 해석학적 전위분포를 유도하였다. 결과적으로 전도중심의 위치에 따라 차단전류는 크게 변화하였으며 이에 따라 문턱전압 및 문턱전압이하 스윙이 변화하는 것을 알 수 있었다.

3상 오프라인 무정전 전원 시스템의 돌입전류 제거 (Inrush Current Elimination for a Three-Phase Off-Line UPS System)

  • ;권병일
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2015년도 제46회 하계학술대회
    • /
    • pp.944-945
    • /
    • 2015
  • Many sensitive loads always rely on UPS systems to maintain continuous power during abnormal utility power conditions. As any disturbance occurs at the utility side, an off-line UPS system takes over the load within a quarter cycle to avoid a blackout. However, the starting of the inverter can root the momentous inrush current for the transformer installed before the load, due to its magnetic saturation. The consequences of this current can be a reduction of line voltage and tripping of protective devices of the UPS system. Furthermore, it can also damage the transformer and decrease its lifetime by increasing the mechanical stresses on its windings. To prevent the inrush current, and to avoid its disruptive effects, this paper proposes an off-line UPS system that eliminates the inrush current phenomenon while powering the transformer coupled loads, using a current regulated voltage source inverter (CRVSI) instead of a typical voltage source inverter (VSI). Simulations have been performed to validate the operation of proposed off-line UPS system.

  • PDF

DGMOSFET의 도핑분포에 따른 상 · 하단 전류분포 및 차단전류 분석 (Analysis on Forward/Backward Current Distribution and Off-current for Doping Concentration of Double Gate MOSFET)

  • 정학기
    • 한국정보통신학회논문지
    • /
    • 제17권10호
    • /
    • pp.2403-2408
    • /
    • 2013
  • 본 연구에서는 이중게이트 MOSFET에 대한 차단전류를 분석하기 위하여 도핑분포함수에 따라 상단과 하단게이트에 의한 전류분포를 분석할 것이다. 분석을 위하여 실험치에 유사한 결과를 얻을 수 있도록 채널도핑농도의 분포함수로써 가우시안함수를 사용하여 유도한 포아송방정식의 이차원 해석학적 전위모델을 이용하여 차단전류를 분석하였다. 특히 소자 파라미터인 채널길이, 채널두께, 게이트산화막 두께 및 채널도핑농도 등을 파라미터로 하여 가우스함수의 이온주입범위 및 분포편차의 변화에 대한 차단전류의 변화를 분석하였다. 분석결과 차단전류는 소자파라미터에 의한 상하단 전류의 변화에 따라 커다란 변화를 보이고 있었으며 특히 채널도핑함수인 가우시안 함수의 형태에 따라서도 큰 변화를 보이고 있다는 것을 관찰할 수 있었다.

GTO의 턴-오프 과도전류와 과도전류가 스위칭에 미치는 영향 (Tail current and its effect on turn-off performance of power GTO thyristor)

  • 장창일;이종;지린견;민원기;김상철;박종문;김은동;김남견
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 1998년도 하계종합학술대회논문집
    • /
    • pp.417-420
    • /
    • 1998
  • In this paper the formation mechanism of tail current is analyzed and its effect on GTO turn-off performance is given. The conclusion is that the large tail current will considerably increase the turn-off loss $E_{off}$ and cause the re-triggering during GTO's off-switching, therefore the best design criterion is that the tail current of power GTO must be as low as possible.w as possible.

  • PDF

Zero-Current-Switching in Full-Bridge DC-DC Converters Based on Activity Auxiliary Circuit

  • Chu, Enhui;Lu, Ping;Xu, Chang;Bao, Jianqun
    • Journal of Power Electronics
    • /
    • 제19권2호
    • /
    • pp.353-362
    • /
    • 2019
  • To address the problem of circulating current loss in the traditional zero-current switching (ZCS) full-bridge (FB) DC/DC converter, a ZCS FB DC/DC converter topology and modulation strategy is proposed in this paper. The strategy can achieve ZCS turn on and zero-voltage and zero-current switching (ZVZCS) turn off for the primary switches and realize ZVZCS turn on and zero-voltage switching (ZVS) turn off for the auxiliary switches. Moreover, its resonant circuit power is small. Compared with the traditional phase shift full-bridge converter, the new converter decreases circulating current loss and does not increase the current stress of the primary switches and the voltage stress of the rectifier diodes. The diodes turn off naturally when the current decreases to zero. Thus, neither reverse recovery current nor loss on diodes occurs. In this paper, we analyzed the operating principle, steady-state characteristics and soft-switching conditions and range of the converter in detail. A 740 V/1 kW, 100 kHz experimental prototype was established, verifying the effectiveness of the converter through experimental results.

The Effects of Lift-Off from Wall Thinning Signal in Pulsed Eddy Current Testing

  • Park, Duck-Gun;Angani, C.S.;Kishore, M.B.;Kim, C.G.;Lee, D.H.
    • Journal of Magnetics
    • /
    • 제17권4호
    • /
    • pp.298-301
    • /
    • 2012
  • In order to know the effect of surface irregularity in the detection of local wall thinning of pipeline using pulsed eddy current (PEC), the lift-off effects on PEC signal have been investigated. Three kinds of parameters in the PEC signal, which is "peak amplitude", "time to peak amplitude" and "time to zero crossing" are analyzed to separate the lift-off effects in the PEC signal. The distance from sensor to the bottom of sample which is the total thickness of combined insulator and sample is kept constant. The magnitude of the differential peak amplitude is increased with increasing sample thickness, the time to peak amplitude is increased with increasing the sample thickness. To determine the effect of lift-off, a number of balanced transient responses combining wall thinning locations and lift-off distances were plotted.