• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.63-66
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• 1998

Prototype MFSFET′s using ferroelectric oxide LiNbO$_3$ as a gate insulator have been successfully fabricated with the help of 2 sheets of metal masks and demonstrated nonvolatile memory operations of the MFSFET′s. The estimated field-effect electron mobility and transconductance on a linear region of the fabricated FET were 600 $\textrm{cm}^2$/V.s and 0.16 mS/mm, respectively. The drain current of the "on" state was more than 4 orders of magnitude larger than the "off" state current at the same "read" gate voltage of 0.5 V, which means the memory operation of the MFSFET. A write voltage as low as $\pm$3 V, which is applicable to low power integrate circuits, was used for polarization reversal.

• Journal of the Korea Institute of Military Science and Technology
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• v.22 no.4
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• pp.536-544
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• 2019

During the assembly and function inspection of missile system, flight simulation process is required. In the conventional flight simulation check of missiles, an inertial navigation system simulator was used to transmit the navigation output data acquired in HILS. There are several disadvantages in terms of check configuration complexity and data synchronization when using the simulator. So we proposed a new flight simulation method that utilizes the nonvolatile built-in memory of the aviation control unit. The data processing procedure and operation procedure of the proposed method for type I and type II missiles are presented. And we analyzed the causes of the difference between proposed method result and the HILS result for type II missile. By comparing the results obtained by the experiments using the proposed method with the results of HILS, the validity of proposed method was confirmed.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.261-268
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• 2018

Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.20.1-20.1
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• 2011

The nano-sized quantum structure has been an attractive candidate for investigations of the fundamental physical properties and potential applications of next-generation electronic devices. Metal nano-particles form deep quantum wells between control and tunnel oxides due to a difference in work functions. The charge storage capacity of nanoparticles has led to their use in the development of nano-floating gate memory (NFGM) devices. When compared with conventional floating gate memory devices, NFGM devices offer a number of advantages that have attracted a great deal of attention: a greater inherent scalability, better endurance, a faster write/erase speed, and more processes that are compatible with conventional silicon processes. To improve the performance of NFGM, metal nanocrystals such as Au, Ag, Ni Pt, and W have been proposed due to superior density, a strong coupling with the conduction channel, a wide range of work function selectivity, and a small energy perturbation. In the present study, bismuth metal nanocrystals were self-assembled within high-k $Bi_2Mg_{2/3}Nb_{4/3}O_7$ (BMN) films grown at room temperature in Ar ambient via radio-frequency magnetron sputtering. The work function of the bismuth metal nanocrystals (4.34 eV) was important for nanocrystal-based nonvolatile memory (NVM) applications. If transparent NFGM devices can be integrated with transparent solar cells, non-volatile memory fields will open a new platform for flexible electron devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.199-203
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• 2017

Mutually-actuated-nano-electromechanical (MA-NEM) memory switches are proposed for scalability improvement. While conventional NEM memory switches have fixed electrode lines, the proposed MA-NEM memory switches have mutually-actuated cantilever-like electrode lines. Thus, MA-NEM memory switches show smaller deformations of beams in switching. This unique feature of MA-NEM memory switches allows aggressive reduction of the beam length while maintaining nonvolatile property. Also, the scalability of MA-NEM memory switches is confirmed by using finite-element (FE) simulations. MA-NEM memory switches can be promising solutions for reconfigurable logic (RL) circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.243.1-243.1
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• 2011

We demonstrate a facile and robust layer-by-layer (LbL) assembly method for the fabrication of nonvolatile resistive switching memory (NRSM) devices based on superparamagnetic nanocomposite multilayers, which allows the highly enhanced magnetic and resistive switching memory properties as well as the dense and homogeneous adsorption of nanoparticles, via nucleophilic substitution reaction (NSR) in nonpolar solvent. Superparamagnetic iron oxide nanoparticles (MP) of about size 12 nm (or 7 nm) synthesized with oleic acid (OA) in nonpolar solvent could be converted into 2-bromo-2-methylpropionic acid (BMPA)-stabilized iron oxide nanoparticles (BMPA-MP) by stabilizer exchange without change of solvent polarity. In addition, bromo groups of BMPA-MP could be connected with highly branched amine groups of poly (amidoamine) dendrimer (PAMA) in ethanol by NSR of between bromo and amine groups. Based on these results, nanocomposite multilayers using LbL assembly could be fabricated in nonpolar solvent by NSR of between BMPA-MP and PAMA without any additional phase transfer of MP for conventional LbL assembly. These resulting superparamagnetic multilayers displayed highly improved magnetic and resistive switching memory properties in comparison with those of multilayers based on water-dispersible MP. Furthermore, NRSM devices, which were fabricated by LbL assembly method under atmospheric conditions, exhibited the outstanding performances such as long-term stability, fast switching speed and high ON/OFF ratio comparable to that of conventional inorganic NRSM devices produced by vacuum deposition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.80-81
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• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a sample of PRAM with thermal protected layer. We have investigated the phase transition behaviors in function of process factor including thermal protect layer. As a result, we have observed that set voltage and duration of protect layer are more improved than no protect layer.

• Journal of the Korean Vacuum Society
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• v.18 no.4
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• pp.302-309
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• 2009

We fabricated a Si nano floating gate memory with Schottky barrier tunneling transistor structure. The device was consisted of Schottky barriers of Er-silicide at source/drain and Si nanoclusters in the gate stack formed by LPCVD-digital gas feeding method. Transistor operations due to the Schottky barrier tunneling were observed under small gate bias < 2V. The nonvolatile memory properties were investigated by measuring the threshold voltage shift along the gate bias voltage and time. We obtained the 10/50 mseconds for write/erase times and the memory window of $\sim5V$ under ${\pm}20\;V$ write/erase voltages. However, the memory window decreased to 0.4V after 104seconds, which was attributed to the Er-related defects in the tunneling oxide layer. Good write/erase endurance was maintained until $10^3$ write/erase times. However, the threshold voltages moved upward, and the memory window became small after more write/erase operations. Defects in the LPCVD control oxide were discussed for the endurance results. The experimental results point to the possibility of a Si nano floating gate memory with Schottky barrier tunneling transistor structure for Si nanoscale nonvolatile memory device.