DOI QR코드

DOI QR Code

Active Page Replacement Policy for DRAM & PCM Hybrid Memory System

DRAM&PCM 하이브리드 메모리 시스템을 위한 능동적 페이지 교체 정책

  • Received : 2018.07.31
  • Accepted : 2018.10.02
  • Published : 2018.10.31

Abstract

Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.

Keywords

References

  1. T.J. Pack, W.Y. Jang, "Large-scale Last- level Cache Design Based on Parallel TLC STT-MRAM," Jounal of KIIT, Vol. 15, No, 12, pp. 77-89, 2017.
  2. P.P. Palangappa, J.Li, K. Mohanram, WOM -Code Solutions for Low Latency and High Endurance in Phase Change Memory," IEEE Transactions on Computers, 2016, Vol. 65, Issue 4, pp. 1025-1040. https://doi.org/10.1109/TC.2015.2506555
  3. A. Awad, B. Kettreing, and Y. Solihin, "Non-volatile memory host controller interface performance analysis in high- performance I/O systems," ISPASS, 2015 IEEE International Symposium on, 2015, pp. 145-153.
  4. J.C. Mogul, E. Argollo, M. Shah, and P. Faraboschi, "Operation system support for NVM+DRAM hybrid main memory," HotOS' 09 Proceedings of the 12th conference on Hot topics in operating systems. 2009, pp.4-14.
  5. H. Seok, Y. Pack, K. W. Park, K. H. Pack, “Efficient Page Caching Algorithm With Prediction and Migration for a Hybrid Main Memory,” ACM, SIGAPP Applied Computing Review, Vol. 11 , No. 4, pp. 38-48, 2011. https://doi.org/10.1145/2107756.2107760
  6. S. I. Jang, S. K. Yoon, "Data Classification Management With its Interfacing Structure for Hybrid SLC/MLC PRAM Main Memory," Jounal of the Computer Journal, Vol. 58, No. 11, pp. 2852-2863, 2015. https://doi.org/10.1093/comjnl/bxu133
  7. S. Y. Lee, H. K. Bahn S. H. Noh, "CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures," IEEE Transactions on Computers, Vol. 63, No. 9, pp. 2187-2200, 2014. https://doi.org/10.1109/TC.2013.98
  8. X. Cai, L. Ju, M. Zhao, Z. Sun, Z. Jia, "A Novel Page Caching Policy for PCM and DRAM of Hybrid Memory Architecture," Proceedings of 13th ICESS., pp.67-73, 2016.
  9. K. M Lee, J. H. Choi, J. W. Kwak, "WAP_LRU: Write Pattern Analysis Rased Hybrid Disk Buffer Management in Flash Storage Systems," IEMEK J. Embed. Sys. Vol. 13, No. 3, pp. 151-160, 2018 (in Korean).
  10. M. K. Qureshi, S. Vijayalakshmi, J. A. Rivers, "Scalable High Performance Main Memory System Using Phase-Change Memory Technology," Proceedings of the 36th annual international symposium on Computer architecture, pp. 24-33, 2009.
  11. K. Y. Park, S. K. Yoon, S. D. Kim, "Selective Data Buffering Module for Unified Hybrid Storage System," Proceedings of 14th International Conference on Computer and Information Science, PP. 173-178, 2015.
  12. C. Chen J. An, "DRAM Write-only-cache for Improving Lifetime of Phase Change Memory," Proceedings of International Midwest Symposium on Circuits and Systems, pp. 1-4, 2016.
  13. N. Nethercote, J. Seward, “Valgrind: A Program Supervision Framwork,” Elsevier Electonc Notes in Theoretical Computer Science, Vol. 89, No. 2, pp. 44-66, 2003. https://doi.org/10.1016/S1571-0661(04)81042-9
  14. Micron Tech, "Phase Change Memory: A new Memory Technology to Enable new Memory Usage Models," Available on: http://www.numonyx.comDocuments/WhitePapers/Numonyx_phaseChangeMemory_WhitePaper.pdf.