• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.135-140
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• 2020

Recently, due to the rapid diffusion of intelligent systems and IoT technologies, power saving techniques in real-time embedded systems has become important. In this paper, we propose P-GA (Parallel Genetic Algorithm), a scheduling algorithm aims at reducing the power consumption of real-time systems in multi-core hybrid memory environments. P-GA improves the Proportional-Fairness (PF) algorithm devised for multi-core environments by combining the dynamic voltage/frequency scaling of the processor with the nonvolatile memory technologies. Specifically, P-GA applies genetic algorithms for optimizing the voltage and frequency modes of processors and the memory types, thereby minimizing the power consumptions of the task set. Simulation experiments show that the power consumption of P-GA is reduced by 2.85 times compared to the conventional schemes.

• Journal of the Korean Vacuum Society
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• v.14 no.1
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• pp.40-48
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• 2005

Bucky shuttle memory systems were investigated by the classical molecular dynamics(MD) simulations. Energetics and operating response of the shuttle-memory-elements u?ere examined by MD simulations of the C/sub 60/ shuttle in the nanomemory systems under various external force fields. Single-nanopeapod type was consisting of three fullerenes encapsulated in (10, 10) boron-nitride nanotube and filled Cu electrode. Studied systems could be applied to nonvolatile memory. MD simulation results showed that the stable bit flops could be achieved from the external force fields of 0.1 eV/Å for single-nanopeapod type.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.4
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• pp.9-18
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• 2013

Flash memory is mostly used on smart devices and embedded systems because of its nonvolatile memory, low power, quick I/O, resistant shock, and other benefits. Generally the typical file systems base on the NAND flash memory are YAFFS2, JFFS2, UBIFS, and etc. In this paper, we had variously made an experiment regarding I/O performance using our schemes and the UBIFS of the latest Linux Kernel. The proposed I/O performance analyses were classified as a sequential access and a random access. Our experiment consists of 6 cases using kmalloc(), vmalloc(), and kmem_cache(). As a result of our experiment analyses, the sequential reading and the sequential rewriting increased by 12%, 11% when the Case 2 has applied vmalloc() and kmalloc() to the UBI subsystem and the UBIFS. Also, the performance improved more by 7.82%, 6.90% than the Case 1 at the random read and the random write.

• Journal of the Korean Ceramic Society
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• v.49 no.6
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• pp.631-636
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• 2012

Conventional SONOS (poly-silicon/oxide/nitride/oxide/silicon) type memory is associated with a retention issue due to the continuous demand for scaled-down devices. In this study, $Al_2O_3/Y_2O_3/SiO_2$ (AYO) multilayer structures using a high-k $Y_2O_3$ film as a charge-trapping layer were fabricated for nonvolatile memory applications. This work focused on improving the retention properties using a $Y_2O_3$ layer with different tunnel oxide thickness ranging from 3 nm to 5 nm created by metal organic chemical vapor deposition (MOCVD). The electrical properties and reliabilities of each specimen were evaluated. The results showed that the $Y_2O_3$ with 4 nm $SiO_2$ tunnel oxide layer had the largest memory window of 1.29 V. In addition, all specimens exhibited stable endurance characteristics (program/erasecycles up to $10^4$) due to the superior charge-trapping characteristics of $Y_2O_3$. We expect that these high-k $Y_2O_3$ films can be candidates to replace $Si_3N_4$ films as the charge-trapping layer in SONOS-type flash memory devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.70-73
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• 2001

MFIS(Metal-ferroelectric-insulator- semiconductor) structures using silicon oxynitride(SiON) buffer layers were fabricatied and demonstrated nonvolatile memory operations. Oxynitride(SiON) films have been formed on p-Si(100) by RTP(rapid thermal process) in O$_2$+N$_2$ ambient at 1100$^{\circ}C$. The gate leakage current density of Al/SiON/Si(100) capacitor was about the order of 10$\^$-8/ A/cm$^2$ at the range of ${\pm}$ 2.5 MV/cm. The C-V characteristics of Al/LiNbO$_3$/SiON/Si(100) capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 24. The memory window width was about 1.2V at the electric field of ${\pm}$300 kV/cm ranges.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.73-74
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• 2006

Ferroelectric thin films have been widely investigated for future nonvolatile memory application. We fabricated the BLT ($(Bi,La)_4Ti_3O_{12}$) films on Si using a STA ($SrTa_2O_6$) buffer layer BLT and STA film were prepared by sol-gel method. Measurement data by XRD and AFM, showed that BLT film and STA films were well crystallized and a good surface morphology. From C-V measurement reward that the Au/BLT/STA/Si structure showed a clockwise hysteresis loop with a memory window of 1.5 V for the bias voltage sweep of ${\pm}5$ V. From results, the Au/BLT/STA/Si structure is useful for FeFETs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.12
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• pp.1283-1288
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• 2004

Metal-ferroelectric-insulator-semiconductor(WFIS) capacitors using rapid thermal annealed LiNbO$_3$/AlN/Si(100) structure were fabricated and demonstrated nonvolatile memory operations. The capacitors on highly doped Si wafer showed hysteresis behavior like a butterfly shape due to the ferroelectric nature of the LiNbO$_3$ films. The typical dielectric constant value of LiNbO$_3$ film in the MFIS device was about 27, The gate leakage current density of the MFIS capacitor was 10$^{-9}$ A/cm$^2$ order at the electric field of 500 kV/cm. The typical measured remnant polarization(2P$_{r}$) and coercive filed(Ec) values were about 1.2 $\mu$C/cm$^2$ and 120 kV/cm, respectively The ferroelectric capacitors showed no polarization degradation up to 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulses of 1 MHz. The switching charges degraded only by 10 % of their initial values after 4 days at room temperature.e.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.41-47
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• 2010

This paper has proposed parallel BCH, one of error correction coding methods which has been used to NAND flash memory for SSD(solid state disk). To alter error correction capability, the proposed design improved reliability on data block has higher error rate as used frequency increasingly. Decoding parallel process bit width is as two times as encoding parallel process bit width, that could reduce decoding processing time, accordingly resulting in one half reduction over conventional ECC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.80-84
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• 2008

We systematically investigated the resistive switching properties of thin $TiO_2$ films on Pt/Ti/$SiO_2$/Si substrates that were embedded with a Co ultra thin layer. An in-situ sputtering technique was used to grow both films without breaking the chamber vacuum. A stable bipolar switching in the current-voltage curve was clearly observed in $TiO_2$ films with an embedded Co ultra thin layer, addressing the high and low resistive state under a bias voltage sweep. We propose that the underlying origin involved in the bipolar switching may be attributed to the interface redox reaction between the Co and $TiO_2$ layers. The improved reproducible switching properties of our novel structures under forward and reverse bias stresses demonstrated the possibility of future non-volatile memory elements in a simple capacitive-like structure.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.