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Parallel BCH Encoding/decoding Method and VLSI Design for Nonvolatile Memory  

Lee, Sang-Hyuk (School of Electrical and Electronics Engineeing, Chung-Ang University)
Baek, Kwang-Hyun (School of Electrical and Electronics Engineeing, Chung-Ang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.5, 2010 , pp. 41-47 More about this Journal
Abstract
This paper has proposed parallel BCH, one of error correction coding methods which has been used to NAND flash memory for SSD(solid state disk). To alter error correction capability, the proposed design improved reliability on data block has higher error rate as used frequency increasingly. Decoding parallel process bit width is as two times as encoding parallel process bit width, that could reduce decoding processing time, accordingly resulting in one half reduction over conventional ECC.
Keywords
VLSI; BCH; SSD (Solid State Disk);
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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