• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11a
• /
• pp.17-20
• /
• 2001

Nonvolatile semiconductor memory devices with reoxidized nitrided oxide(RONO) gate dielectric were fabricated, and nitrogen distribution and bonding species which contributing memory characteristics were analyzed. Also, memory characteristics of devices according to anneal temperatures were investigated. The devices were fabricated by 0.35$\mu\textrm{m}$ retrograde twin well CMOS processes. The processes could be simple by in-situ process of nitridation anneal and reoxidation. The nitrogen distribution and bonding state of gate dielectric were investigated by Dynamic Secondary Ion Mass Spectrometry(D-SIMS), Time-of-Flight Secondary ton Mass Spectrometry(ToF-SIMS), and X-ray Photoelectron Spectroscopy(XPS). Nitrogen concentrations are proportional to nitridation anneal temperatures and the more time was required to form the same reoxidized layer thickness. ToF-SIMS results show that SiON species are detected at the initial oxide interface and Si$_2$NO species near the new Si-SiO$_2$ interface that formed after reoxidation. As the anneal temperatures increased, the device showed worse retention and degradation properties. These could be said that nitrogen concentration near initial interface is limited to a certain quantity, so excess nitrogen are redistributed near the Si-SiO$_2$ interface and contributed to electron trap generation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.11a
• /
• pp.53-53
• /
• 2009

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were used as engineered tunneling barriers. The VARIOT type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.384-384
• /
• 2012

We report nonvolatile memory properties of poly (3, 4-ethylenedioxythiophene) (PEDOT) thin films grown by vapor phase polymerization using FeCl3 as an oxidant. Liquid-bridge-mediated transfer method was employed to remove FeCl3 for generation of pure PEDOT thin films. From the electrical measurement of memory device, we observed voltage induced bipolar resistive switching behavior with ON/OFF ratio of 103 and reproducibility of more than 103 dc sweeping cycles. ON and OFF states were stable up to 104 seconds without significant degradation. Cyclic voltammetry data illustrates resistive switching effect can be attributed to formation and rupture of conducting paths due to oxidation and reduction of PEDOT. The maximum current before reset process was found to be increase linearly with increase in compliance current applied during set process.

• Journal of the Korean Ceramic Society
• /
• v.41 no.4
• /
• pp.273-276
• /
• 2004

Report ferroelectric memories based on 0.35$\mu\textrm{m}$ CMOS technology ensuring ten-year retention and imprint at 175$^{\circ}C$. This excellent reliability resulted from newly developed BT-based ferroelectric films with superior reliability performance at high temperatures, and also resulted from robust integration schemes free from ferroelectric degradation due to process impurities such as moisture and hydrogen. The superior reliabilities at high temperature of ferroelectric memories using BT-based films are due to the random orientation by special bake treatments.

• Electrical & Electronic Materials
• /
• v.7 no.2
• /
• pp.165-175
• /
• 1994

1967년 Wegener등과 Khang등이 각각 구조 및 동작원리가 다른 비휘발성 반도체 메모리(nonvolatile semiconductor memory)를 최초로 개발, 도입한 이후 3세대째를 보내고 있는 현재, 메모리는 반도체산업의 선봉으로써 여전히 공정기술(processing technology)을 이끌며, 시장점유율, 응용범위등에서 주도적 위치를 차지하고 있다. 한편, 최근의 컴퓨터 시스템은 소형화, 저전력화, 고속화, 내충격성 등 기술적 측면에서 뿐만 아니라 소프트웨어적으로도 급격히 발전하고 있다. 이에 따라 메모리부분에 있어서도 기존의 자기 하드디스크 메모리(magnetic hard disk memory)의 한계를 극복하기 위해서 반도체 메모리로서 대체가 더욱 요구되고 있다. 이와같은 상황에서 EEPROM(electrically erasable and programmable ROM)은 상주 시스템내에서도 전기적 방법에 의해 사용자가 임으로 기록/소거(write/erase)할 수 있을 뿐만 아니라 전원이 제거된 상테에서도 기억상태를 유지할 수 있는 비휘발성이라는 점에서 차세대 반도체 메모리 부문의 주역으로서 주목받고 있다. 따라서, 본 고에서는 20세기를 보내며 반도체메모리의 새로운 장을 열어가는 EEPROM의 기술현황 및 전망에 관해 살펴보고자 한다.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.863-866
• /
• 2003

Recently, there has been growing interests in the magneto-resistive random access memory (MRAM) because of its great potential as a future nonvolatile memory. In this paper, a CMOS macro-model for MRAM cell based on a twin cell structure is proposed. The READ and WRITE operations of the MTJ cell can be emulated by adopting data latch and switch blocks. The behavior of the circuit is confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process. We expect the macro model can be utilized to develope the core architecture and the peripheral circuitry. It can also be used for the characterization and the direction of the real MTJ cells.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.238.1-238.1
• /
• 2014

이번 연구는 system-on-panel에 적용하기 위한 비휘발성 메모리의 메모리 윈도우 특성 향상에 관한 연구이다. 이를 위해 SiO2/SiNX/SiOXNY의 메모리 구조를 이용하였으며, 채널층으로 투명한 비정질 인듐-주석-아연-산화물을 이용하였다. N형 물질의 특성인 수많은 전자로 인해 erasing의 어려움이 발생하는데 이는 빛과 전압의 동시 인가로 해결하였다. 전하트랩층은 비휘발성 메모리에서 가장 널리 이용되는 질화막을 이용하였으며, SiH4과 NH3의 비율은 8대 1에서 1대 2까지 이용하였다. 이번 연구에서 SiH4과 NH3의 비율이 2대 1일 때 쓰기 전압 +13V와 지우기 전압 -6V에서 약 3.7V의 높은 메모리 윈도우를 얻을 수 있었다.

• Electrical & Electronic Materials
• /
• v.4 no.3
• /
• pp.259-266
• /
• 1991

1.5.mu.m의 찬넬길이를 갖는 short channel 비휘발성 SNOSFET 기억소자를 기존의 CMOS 1 Mbit 공정기술을 이용하여 제작하고 I$_{d}$-V$_{d}$ 및 I$_{d}$- V$_{g}$특성과 스윗칭 및 기억유지특성을 조사하였다. 그 결과 제작한 소자는 논리회로 설계에 적절한 전도특성을 가졌으며 스윗칭시간은 인가전압의 크기에 의존함을 보였다. 그리고 3V의 memory window 크기를 얻기 위해서 V$_{w}$ =+34V, t$_{w}$ =50.mu.sec 및 V$_{e}$=-34V, t$_{e}$=500.mu.sec의 펄스전압으로 각각 write-in과 erase할 수 있었다. 또한 기억상태는 10년이상 유지할 수 있음을 알 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.24 no.4
• /
• pp.325-327
• /
• 2011

In this paper, nonvolatile nano-floating gate memory devices are fabricated with ZnO nanowires and Al nanoparticles on a $SiO_2/Si$ substrate. Al nanoparticles used as floating gate nodes are formed by the sputtering method. The fabricated device exhibits a threshold voltage shift of -1.5 V. In addition, we investigate the endurance and retention characteristics of the nano-floating gate memory device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.1
• /
• pp.7-11
• /
• 1998

In this paper, a new synapse cell with nonvolatile SONOS semiconductor memory device is proposed and it's fundamental function electronically implemented SONOS NVSM has shown characteristics that the memory value, synaptic weights, can be increased or decreased incrementally. A novel SONOS synapse is used to read out the stored analog value. For the purpose of synapse implementation using SONOS NVSM, this work has investigated multiplying characteristics including weight updating characteristics and neuron output characteristics. It is concluded that SONOS synapse cell has good agreement for use as a synapse in artificial neural networks.