• 전기전자학회논문지
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• 제21권3호
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• pp.264-267
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• 2017

본 논문에서는 잡음 제거 회로를 이용하여 공급 전원 제거 비를 향상시킨 LDO(Low drop-out) 레귤레이터를 제안하였다. LDO 레귤레이터 내부의 오차증폭기와 패스 트랜지스터 사이에 잡음 제거 회로를 두어 전압 라인에서 들어오는 노이즈에 패스 트랜지스터가 받는 영향을 줄일 수 있게 설계하였으며, 기존의 LDO 레귤레이터와 동일한 레귤레이션 특성을 갖도록 했다. 제안한 회로는 0.18um 공정을 사용하였고 Cadence의 Virtuoso, Spectre 시뮬레이터를 사용하였다.

• 한국정밀공학회지
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• 제16권1호통권94호
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• pp.61-67
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• 1999

A laser Doppler vibrometer based on the laser heterodyne interferometry is employed to measure the vibration velocity of vibrating objects. In this paper, we propose a real time analog signal processor of a laser Doppler vibrometer to reduce the degradation of Doppler signals mainly caused by environmental noises. In the proposed real time signal processor of an laser Doppler vibrometer, a pre-processor and a logical motion direction detector are designed to reduce the detection errors of the object motion direction. Also, a noise detection and rejection circuit is designed to reject the unfiltered noises.

• ETRI Journal
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• 제34권4호
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.

• IEIE Transactions on Smart Processing and Computing
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• 제4권3호
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• pp.152-157
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• 2015

Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.300-308
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• 2010

This paper describes the development of a low-power electrocardiogram (ECG) touch sensor intended for the use with two dry metal electrodes. An equivalent ECG extraction circuit model encountered in a ground-free two-electrode configuration is investigated for an optimal sensor read-out circuit design criteria. From the equivalent circuit model, (1) maximum sensor resolution is derived based on the electrode's background thermal noise, which originates from high electrode-skin contact impedance, together with the input referred noise of instrumentation amplifier (IA), (2) 60 Hz electrostatic coupling from mains and motion artifact are also considered to determine minimum requirement of common mode rejection ratio (CMRR) and input impedance of IA. A dedicated ECG read-out front end incorporating chopping scheme is introduced to provide an input referred circuit noise of 1.3 ${\mu}V_{rms}$ over 0.5 Hz ~ 200 Hz, CMRR of IA > 100 dB, sensor resolution of 7 bits, and dissipating only 36 ${\mu}W$. Together with 8 bits synchronous successive approximation register (SAR) ADC, the sensor IC chip is implemented in 0.18 ${\mu}m$ CMOS technology and integrated on a 5 cm $\times$ 8 cm PCB with two copper patterned electrodes. With the help of proposed touch sensor, ECG signal containing QRS complex and P, T waves are successfully extracted by simply touching the electrodes with two thumbs.

• 전기전자학회논문지
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• 제23권2호
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• pp.722-726
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• 2019

본 논문에서는 고주파 영역에서의 전원잡음제거 (PSR) 특성이 개선된 low drop-out (LDO) 레귤레이터를 제안한다. 특히, PMOS 전력 스위치의 유한한 출력저항을 관통하는 고주파 전원잡음을 상쇄하기 위해 출력저항이 큰 NMOS 트랜지스터를 보상 회로로 추가하였다. 보상 트랜지스터에 의한 전원잡음제거는 해석적으로 설명하여 개선에 대한 방향을 제시하였다. $0.35{\mu}m$ 표준 CMOS 공정으로 회로를 제작하고 Spectre 시뮬레이션을 수행하여 10MHz에서 기존의 LDO 레귤레이터 대비 26dB의 PSR 개선을 확인하였다.

• 한국전자파학회논문지
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• 제19권3호
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• pp.343-351
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• 2008

본 논문에서는 FPC(Flexible Printed Circuit) 케이블에 적층된 나선형 인덕터를 내장하여 다기능 케이블을 위한 공통 모드 필터를 제안하였다. 공통 모드 필터가 내장된 FPC 케이블은 별도의 SMD(Surface Mounted Device) 필터 없이 연성 케이블과 공통 모드 차단 특성을 가짐으로서, 다기능 케이블이라는 새로운 개념을 제시한다. 내장된 공통 모드 필터는 광대역의 공통 모드 차단 대역을 가지고 손실이 큰 페라이트와 같은 자성 물질을 사용하지 않아 차동 모드 삽입 손실 및 반사 손실이 향상되었다. 3-turn 인덕터를 가진 공통 모드 필터는 공통 모드차단 대역이 $0.4{\sim}3.12GHz$이며, 페라이트를 적용한 상용 LTCC(Low Temperature Co-fire Ceramic) 공통 모드 필터에 비해 3 GHz에서 1.95 dB, 8 GHz에서 6.97 dB의 향상된 차동 모드 삽입 손실을 갖는다.

• 한국산학기술학회논문지
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• 제12권6호
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• pp.2729-2734
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• 2011

본 논문에서는 DC 정합회로를 갖는 능동 Replica LDO 레귤레이터에 대하여 나타내었다. Replica단과 출력단의 DC전압을 정합하기 위하여 DC정합회로를 설계하였다. 능동 Replica LDO 레귤레이터의 PSR특성은 일반적인 레귤레이터 보다 큰 값을 가질 수 있다. 설계된 DC정합회로는 Replica 레귤레이터에서 발생할 수 있는 단점을 줄여준다. 또한 전체회로를 능동회로로 설계함으로써 칩면적을 줄이고 수동저항을 사용할 때 발생하는 열잡음을 제거할 수 있다. 0.35um CMOS 파라미터를 사용하여 HSPICE 시뮬레이션한 결과, DC정합회로를 이용하여 설계된 레귤레이터의 PSR특성은 -28dB@10Hz로써 DC정합회로를 사용하지 않는 일반적인 레귤레이터의 -17dB@10Hz보다 개선될 수 있음을 확인하였다. 레귤레이터의 DC출력 전압은 3V이다.

• Journal of electromagnetic engineering and science
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• 제10권1호
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• pp.25-27
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• 2010

This paper presents a gain and phase mismatch calibration technique for an image-reject RF receiver. The gain mismatch is calibrated by directly measuring the output signal amplitudes of two signal paths. The phase mismatch is calibrated by measuring the output amplitude of the final IF output at the image band. The calibration of the gain and phase mismatch is performed at power-up, and the normal operation of the RF receiver does not interfere with the mismatch calibration circuit. To verify the proposed technique, a 2.4-GHz Weaver image-reject receiver with the gain and phase mismatch calibration circuit is implemented in a 0.18-${\mu}m$ CMOS technology. The overall receiver achieves a voltage gain of 45 dB and a noise figure of 4.8 dB. The image rejection ratio(IRR) is improved from 31 dB to 59.76 dB even with 1 dB and $5^{\circ}$ mismatch in gain and phase, respectively.

• ETRI Journal
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• 제42권4호
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• pp.549-561
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• 2020

We developed a 0.1-㎛ metamorphic high electron mobility transistor and fabricated a W-band monolithic microwave integrated circuit chipset with our in-house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz-108 GHz band and achieved excellent spurious suppression. A low-noise amplifier (LNA) with a four-stage single-ended architecture using a common-source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W-band image-rejection mixer (IRM) with an external off-chip coupler was also designed. The IRM provided a conversion gain of 13 dB-17 dB for RF frequencies of 80 GHz-110 GHz and image-rejection ratios of 17 dB-19 dB for RF frequencies of 93 GHz-100 GHz.