• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1763-1768
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• 2016

This paper presents the electrical characteristics of the gallium nitride (GaN) current aperture vertical electron transistor (CAVET) by using two-dimensional (2-D) technology computer-aided design (TCAD) simulations. The CAVETs are considered as the alternative device due to their high breakdown voltage and high integration density in the high-power applications. The optimized design for the CAVET focused on the electrical performances according to the different gate-source length ($L_{GS}$) and aperture length ($L_{AP}$). We analyze DC and RF parameters inducing on-state current ($I_{on}$), threshold voltage ($V_t$), breakdown voltage ($V_B$), transconductance ($g_m$), gate capacitance ($C_{gg}$), cut-off frequency ($f_T$), and maximum oscillation frequency ($f_{max}$).

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.785-789
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• 2005

Low temperature deposition of silicon and silicon nitride films by catalytic CVD technique was studied for application to thin film transistors on plastic substrates for flexible AMOLEDs. The substrate temperature initially held at room temperature, and was controlled successfully below $150^{\circ}C$ during the entire deposition process. Amorphous silicon films having good adhesion, good surface morphology and sufficiently low content of atomic hydrogen were obtained and could be successfully crystallized using excimer laser without a prior dehydrogenation step. $SiN_x$ films showed a good refractive index, a high deposition rate, a moderate breakdown field and a dielectric constant. The Cat-CVD silicon and silicon nitride films can be good candidates for fabricating thin films transistors on plastic substrates to drive active-matrix organic light emitting display.

• Transactions on Electrical and Electronic Materials
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• v.12 no.4
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• pp.148-151
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• 2011

We designed and fabricated aluminium gallium nitride (AlGaN)/GaN high electron mobility transistors (HEMTs) with stable reverse blocking characteristics established by employing a selective fluoride plasma treatment on the drainside gate edge region where the electric field is concentrated. Implanted fluoride ions caused a depolarization in the AlGaN layer and introduced an extra depletion region. The overall contour of the depletion region was expanded along the drift region. The expanded depletion region distributed the field more uniformly and reduced the field intensity peak. Through this field modulation, the leakage current was reduced to 9.3 nA and the breakdown voltage ($V_{BR}$) improved from 900 V to 1,400 V.

• Proceedings of the Materials Research Society of Korea Conference
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• 1993.05a
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• pp.89-90
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• 1993

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.981-984
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• 2005

This study is to realize its threshold voltage shift after programming operation in charge trap type SONOS memory by simulation. SONOS devices are charge trap type nonvolatile memory devices in which charge storage takes place in traps in the nitride-blocking oxide interface and the nitride layer. For simulation of their threshold voltage as a function of the memory states, traps in the nitride layer have to be defined. However, trap models in the nitride layer are not developed in commercial simulator. So, we propose a new method that can simulate their threshold voltage shift by an amount of charges induced to the electrodes as a function of a programming voltages and times as define two electrodes in the tunnel oxide-nitride interface and the nitride-blocking oxide interface of SONOS structures.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.6
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• pp.28-33
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• 1985

ISFETS for physiological applications have been developed using the techniques for integrated circuit fabrication. The silicon nitride layer was used as a H+ sensing membrane. However, K+, Na+ and Ca++ sensing ISFETS were fabricated by forming tach specification sensing membranes over the silicon nitride gate insulator. The sensitivities of the fabricated devices were very good. The typical values of measured sentivities were iEmV/pH, 42mv1, pH,5 gmV/pNa and 28mv1p0a. However, the selectivity and stability should be somewhat improved for practical physiological uses with good reliability. The response times were, less than one second, short enough for the practical uses in physiological applications.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1489-1498
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• 2015

Gallium nitride (GaN)-based power switching devices, such as high-electron-mobility transistors (HEMT), provide significant performance improvements in terms of faster switching speed, zero reverse recovery, and lower on-state resistance compared with conventional silicon (Si) metal-oxide-semiconductor field-effect transistors (MOSFET). These benefits of GaN HEMTs further lead to low loss, high switching frequency, and high power density converters. Through simulation and experimentation, this research thoroughly contributes to the understanding of performance characterization including the efficiency, loss distribution, and thermal behavior of a 160-W GaN-based synchronous boost converter under various output voltage, load current, and switching frequency operations, as compared with the state-of-the-art Si technology. Original suggestions on design considerations to optimize the GaN converter performance are also provided.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.44-50
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• 1993

In an attempt to improve the electrical characteristics of tantalum pentoxide dielectric film, silicon substrate was reacted with a nitrogen plasma to form a silicon nitride of 50.angs. and then tantalum pentoxide thin films were formed by reactive sputtering in the same chamber. Breakdown field and leakage current density were measured to be 2.9 MV/cm and 9${\times}10^{8}\;A/cm^{2}$ respectively in these films whose thickness was about 180.angs.. With annealing at rectangular waveguides with a slant grid are investigated here. In particular, 900.deg. C in oxygen ambient for 100 minutes, breakdown field and leakage current density were improved to be 4.8 MV/cm and 1.61.6${\times}10^{8}\;A/cm^{2}$ respectively. It turned out that the electrical characteristics could also be improved by oxygen plasma post-treatment and the conduction mechanism at high electric field proved to be Schottky emission in these double-layered films.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.37-43
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• 2008

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experiment that analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.9-16
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• 1999

When the conventional IPD (inter-poly-dielctrics) layer with ONO(oxide-nitride-oxide) structure was used in the Flash EEPROM cell, its data retention characteristics were significanfly degraded because the top oxide of the ONO layer was etched off due to the cleaning process used in the gate oxidation process for the peripheral MOSFETs. When the IPD layer with the ONON(oxide-nitride-oxide-nitride) was used there, however, its data retention characteristics were much improved because the top nitride of the ONON layer protected the top oxide from being etched in the cleaning process. For the modelling of the data retention characteristics of the Flash EEPROM cell with the ONON IPD layer, the decrease of the threshold voltage cue to the charge loss during the bake was here given by the empirical relation ${\Delta}V_t\; = \;{\beta}t^me^{-ea/kT}$ and the values of the ${\beta}$=184.7, m=0.224, Ea=0.31 eV were obtained with the experimental measurements. The activation energy of 0.31eV implies that the decrease of the threshold voltage by the back was dur to the movement of the trapped electrons inside the inter-oxide nitride layer. On the other hand, the results of the computer simulation using the model were found to be well consistent with the results of the electrical measurements when the thermal budget of the bake was not high. However, the latter was larger then the former in the case of the high thermal budger, This seems to be due to the leakage current generated by the extraction of the electrons with the bake which were injected into the inter-oxide niride later and were trapped there during the programming, and played the role to prevent the leakage current. To prevent the generation of the leakage current, it is required that the inter-oxide nitride layer and the top oxide layer be made as thin and as thick as possible, respectively.