• Journal of Institute of Control, Robotics and Systems
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• v.21 no.5
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• pp.477-481
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• 2015

Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. "Memristor", which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.2
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• pp.111-118
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• 2001

In this paper, in order to implement the multi-layered perceptron neural network using pure digital logic circuit model, we propose the new logic neuron structure, the digital canonical multi-layered logic neural network structure, and the multi-stage multi-layered logic neural network structure for pattern recognition applications. And we show that the proposed approach provides an incremental additive learning algorithm, which is very simple and effective.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.7 no.2
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• pp.13-18
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• 2013

In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.

• Journal of Korea Multimedia Society
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• v.13 no.4
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• pp.504-511
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• 2010

In this paper, we propose the face region recognition system for City-Security CCTV(Closed Circuit Television) using hippocampal neural network which is modelling of human brain's hippocampus. This system is composed of feature extraction, learning and recognition part. The feature extraction part is constructed using PCA(Principal Component Analysis) and LDA(Linear Discriminants Analysis). In the learning part, it can label the features of the image-data which are inputted according to the order of hippocampal neuron structure to reaction-pattern according to the adjustment of a good impression in a dentate gyrus and remove the noise through the auto-associative memory in the CA3 region. In the CA1 region receiving the information of the CA3, it can make long-term memory learned by neuron. Experiments confirm the each recognition rate, that are shape change and light change. The experimental results show that we can compare a feature extraction and learning method proposed in this paper of any other methods, and we can confirm that the proposed method is superior to existing methods.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• Annals of Clinical Neurophysiology
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• v.14 no.2
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• pp.64-71
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• 2012

Background: It is generally accepted that upper motor neuron (UMN) lesion can alter lower motor neuron (LMN) function by the plasticity of neural circuit. However there have been only few researches regarding the axonal excitability of LMN after UMN injury especially during the acute stage. The aim of this study was to investigate the nerve excitability properties of the LMNs following an acute to subacute supratentorial corticospinal tract lesion. Methods: An automated nerve excitability test (NET) using the threshold tracking technique was utilized to measure multiple excitability indices in median motor axons of 15 stroke patients and 20 controls. Testing of both paretic and non-paretic side was repeated twice, during the acute stage and subacute stage. The protocols calculated the strength-duration time constant from the duration-charge curve, parameters of threshold electrotonus (TE), the current-threshold relationship from sequential sub-threshold current, and the recovery cycle from sequential supra-threshold stimulation. Results: On the paretic side, compared with the control group, significant decline of superexcitablity and increase in the relative refractory period were observed during the subacute stage of stroke. Additionally, despite the absence of statistical significance, a mildly collapsing in ('fanning in') of the TE was found. Conclusions: Our results suggest that supratentorial brain lesions can affect peripheral axonal excitability even during the early stage. The NET pattern probably suggests background membrane depolarization of LMNs. These features could be associated with trans-synaptic regulation of UMNs to LMNs as one of the "neural plasticity" mechanisms in acute brain injury.

• BioChip Journal
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• v.12 no.4
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• pp.332-339
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• 2018

The future neuro-prosthetic devices would be required spikes data monitoring through sub-nanoscale transistors that enables to neuroscientists and clinicals for scalable, wireless and implantable applications. This research investigates the spikes monitoring through integrated CNT front-end amplifier for neuro-prosthetic diagnosis. The proposed carbon nanotube-based architecture consists of front-end amplifier (FEA), integrate fire neuron and pseudo resistor technique that observed high electrical performance through neural activity. A pseudo resistor technique ensures large input impedance for integrated FEA by compensating the input leakage current. While carbon nanotube based FEA provides low-voltage operation with directly impacts on the power consumption and also give detector size that demonstrates fidelity of the neural signals. The observed neural activity shows amplitude of spiking in terms of action potential up to $80{\mu}V$ while local field potentials up to 40 mV by using proposed architecture. This fully integrated architecture is implemented in Analog cadence virtuoso using design kit of CNT process. The fabricated chip consumes less power consumption of $2{\mu}W$ under the supply voltage of 0.7 V. The experimental and simulated results of the integrated FEA achieves $60G{\Omega}$ of input impedance and input referred noise of $8.5nv/{\sqrt{Hz}}$ over the wide bandwidth. Moreover, measured gain of the amplifier achieves 75 dB midband from range of 1 KHz to 35 KHz. The proposed research provides refreshing neural recording data through nanotube integrated circuit and which could be beneficial for the next generation neuroscientists.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.43-50
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• 2005

In this paper, quaternary logic gates using Down literal circuit(DLC) has been designed, and then synchronous Quaternary un/down counter using those gates has been proposed The proposed counter consists of T-type quaternary flip flop and 1-of-2 threshold-t MUX, and T-type quaternary flip flop consists of D-type quaternary flip flop and quaternary logic gates(modulo-4 addition gates, Quaternary inverter, identity cell, 1-of-4 MUX). The simulation result of this counter show delay time of 10[ns] and power consumption of 8.48[mW]. Also, assigning the designed counter to MVL(Multiple-valued Logic) circuit, it has advantages of the reduced interconnection and chip area as well as easy expansion of digit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.5
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• pp.1-9
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• 2012

Memristor which is known as fourth basic circuit element has been developed recently but its electrical characteristics are not still fully understood. Memristor has the incremental and decremental feature of the resistance depending upon the connected polarities. Also, its operational behavior become diverse depending on its connection topologies. In this work, electrical characteristics of diverse types of serial and parallel connections are investigated using the HP $TiO_2$ model. The characteristics are analyzed with pinched hystersis loops on the V-I plane when sine input signal is applied. The results of the work would be utilized usefully for analyzing the characteristics of memristor element and applications to logic circuit and neuron cells.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.14-24
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• 2002

In this paper, a design of the pulsewidth-modulation(PWM) neural network with both retrieving and learning function is proposed. In the designed PWM neural system, the input and output signals of the neural network are represented by PWM signals. In neural network, the multiplication is one of the most commonly used operations. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Thus, the designed neural network only occupies the small chip area. By applying some circuit design techniques to reduce the nonideal effects, the designed circuits have good linearity and large dynamic range. Moreover, the delta learning rule can easily be realized. To demonstrate the learning capability of the realized PWM neural network, the delta learning nile is realized. The circuit with one neuron, three synapses, and the associated learning circuits has been designed. The HSPICE simulation results on the two learning examples on AND function and OR function have successfully verified the function correctness and performance of the designed neural network.