• Journal of Sensor Science and Technology
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• v.29 no.5
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• pp.354-359
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• 2020

The high vacuum hermetic sealing technique ensures excellent performance of MEMS resonators. For the high vacuum hermetic sealing, the customization of anodic bonding equipment was conducted for the glass/Si/glass triple-stack anodic bonding process. Figure 1 presents the schematic of the MEMS resonator with triple-stack high-vacuum anodic bonding. The anodic bonding process for vacuum sealing was performed with the chamber pressure lower than 5 × 10^-6 mbar, the piston pressure of 5 kN, and the applied voltage was 1 kV. The process temperature during anodic bonding was 400 ℃. To maintain the vacuum condition of the glass cavity, a getter material, such as a titanium thin film, was deposited. The getter materials was active at the 400 ℃ during the anodic bonding process. To read out the electrical signals from the Si resonator, a vertical feed-through was applied by using through glass via (TGV) which is formed by sandblasting technique of cap glass wafer. The aluminum electrodes was conformally deposited on the via-hole structure of cap glass. The TGV process provides reliable electrical interconnection between Si resonator and aluminum electrodes on the cap glass without leakage or electrical disconnection through the TGV. The fabricated MEMS resonator with proposed vacuum packaging using three-layer anodic bonding process has resonance frequency and quality factor of about 16 kHz and more than 40,000, respectively.

• Journal of Radiation Protection and Research
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• v.47 no.3
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• pp.134-142
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• 2022

Background: This study investigated the characteristics of optically stimulated luminescence dosimeters (OSLDs) with fully filled deep electron/hole traps in the kV energy ranges. Materials and Methods: The experimental group consisted of InLight nanoDots, whose deep electron/hole traps were fully filled with 5 kGy pre-irradiation (OSLD_exp), whereas the non-pre-irradiated OSLDs were arranged as a control group (OSLD_cont). Absorbed doses for 75, 80, 85, 90, 95, 100, and 105 kVp with 200 mA and 40 ms were measured and defined as the unit doses for each energy value. A bleaching device equipped with a 520-nm long-pass filter was used, and the strong beam mode was used to read out signal counts. The characteristics were investigated in terms of fading, dose sensitivities according to the accumulated doses, and dose linearity. Results and Discussion: In OSLD_exp, the average normalized counts (sensitivities) were 12.7%, 14.0%, 15.0%, 10.2%, 18.0%, 17.9%, and 17.3% higher compared with those in OSLD_cont for 75, 80, 90, 95, 100, and 105 kVp, respectively. The dose accumulation and bleaching time did not significantly alter the sensitivity, regardless of the filling of deep traps for all radiation qualities. Both OSLD_exp and OSLD_cont exhibited good linearity, by showing coefficients determination (R²) > 0.99. The OSL sensitivities can be increased by filling of deep electron/hole traps in the energy ranges between 75 and 105 kVp, and they exhibited no significant variations according to the bleaching time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.7-8
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• 2007

We investigated the characteristics of UTB-SOI pMOSFETs with SOI thickness ($T_{SOI}$) ranging from 10 nm to 1 nm and evaluated the dependence of electrical characteristics on the silicon surface orientation. As a result, it is found that the subthreshold characteristics of (100)-surface UTB-SOI pMOSFETs were superior to (110)-surface. However, the hole mobility of (110)-surface were larger than that of (100)-surface. The enhancement of effective hole mobility at the effective field of 0.1 MV/ccm was observed from 3-nm to 5-nm SOI thickness range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.263-263
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• 2010

High temperature annealing is required to synthesize graphene using CVD. When thin metal catalyst is used for the synthesis, the high temperature pre-annealing makes the thin catalyst highly agglomerated. We investigated the agglomeration effect on the shape of the synthesized graphene. It is found that high temperature annealing makes randomly distributed many hole or blister on metal catalyst, and the synthesized graphene features floral pattern around the hole. The floral patterns of graphene turned out to be multi-layers and higher D peaks in raman spectrum.

• International Journal of Precision Engineering and Manufacturing
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• v.6 no.2
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• pp.5-11
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• 2005

Among the micro machining techniques, micro EDM is generally used for machining micro holes, pockets, and micro structures on difficult-cut-materials. Micro EDM parameters such as applied voltage, capacitance, peak current, pulse width, duration time are very important to fabricate the tool electrode and produce the micro structures. Developed micro EDM machine is composed of a 3-axis driving system and RC circuit equipped with pulse generator. In this paper, using micro EDM machine, the characteristics of micro EDM process are investigated and it is applied to micro holes, slots, and pockets machining. Through experiments, relations between machined surface and voltages and between MRR and feedrate are investigated. Also the trends of tool wear are investigated in case of hole and slot machining.

• Journal of Korean Vacuum Science & Technology
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• v.4 no.2
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• pp.44-46
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• 2000

Near-field photocurrent experiments were performed for GaAs/AIGaAs MQWs at room temperature. Heavy hole and light hole related peaks are clearly resolved even under extremely low power of near-field excitation. By scanning laterally 2 $\mu\textrm{m}$${\times}$2 $\mu\textrm{m}$ area on the surface, minority carrier diffusion process in the well region was qualitatively studied.

• Journal of Sensor Science and Technology
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• v.10 no.5
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• pp.292-303
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• 2001

This work reports the tunneling effects of the lateral field emitters. Tunneling effect is applicable to the VMFS(vacuum magnetic field sensors). VMFS uses the fact that the trajectory of the emitted electrons are curved by the magnetic field due to Lorentz force. Polysilicon was used as field emitters and anode materials. Thickness of the emitter and the anode were $2\;{\mu}m$, respectively. PSG(phospho-silicate-glass) was used as a sacrificial layer and it was etched by HF at a releasing step. Cantilevers were doped with $POCl_3(10^{20}cm^{-3})$. $2{\mu}m$-thick cantilevers were fabricated onto PSG($2{\mu}m$-thick). Sublimation drying method was used at releasing step to avoid stiction. Then, device was vacuum sealed. Device was fixed to a sodalime-glass #1 with silver paste and it was wire bonded. Glass #1 has a predefined hole and a sputtered silicon-film at backside. The front-side of the device was sealed with sodalime-glass #2 using the glass frit. After getter insertion via the hole, backside of the glass #1 was bonded electrostatically with the sodalime-glass #3 at $10^{-6}\;torr$. After sealing, getter was activated. Sealing was successful to operate the tunneling device. The packaged VMFS showed very small reduced emission current compared with the chamber test prior to sealing. The emission currents were changed when the magnetic field was induced. The sensitivity of the device was about 3%/T at about 1 Tesla magnetic field.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.115-120
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• 2008

Carrier velocity in the MOSFET channel is the main driving force for improved transistor performance with scaling. We report measurements of the drift velocity of electrons and holes in silicon inversion layers. A technique for extracting effective carrier velocity which is a more accurate extraction method based on the actual inversion charge measurement is used. This method gives more accurate result over the whole range of $V_{ds}$, because it does not assume a linear approximation to obtain the inversion charge and it does not limit the range of applicable $V_{ds}$. For a very short channel length device, the electron velocity overshoot is observed at room temperature in 37 nm MOSFETs while no hole velocity overshoot is observed down to 36 nm. The electron velocity of short channel device was found to be strongly dependent on the longitudinal field.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.246-246
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• 2010

As the trench width in the interconnect technology decreases down to nano-scale below 50 nm, superconformal gap-filling process of Cu becomes very critical for Cu interconnect. Obtaining superconfomral gap-filling of Cu in the nano-scale trench or via hole using MOCVD is essential to control nucleation and growth of Cu. Therefore, nucleation of Cu must be suppressed near the entrance surface of the trench while Cu layer nucleates and grows at the bottom of the trench. In this study, suppression of Cu nucleation was achieved by treating the Ru barrier metal surface with capacitively coupled hydrogen plasma. Effect of hydrogen plasma pretreatment on Cu nucleation was investigated during MOCVD on atomic-layer deposited (ALD)-Ru barrier surface. It was found that the nucleation and growth of Cu was affected by hydrogen plasma treatment condition. In particular, as the plasma pretreatment time and electrode power increased, Cu nucleation was inhibited. Experimental data suggests that hydrogen atoms from the plasma was implanted onto the Ru surface, which resulted in suppression of Cu nucleation owing to prevention of adsorption of Cu precursor molecules. Due to the hydrogen plasma treatment of the trench on Ru barrier surface, the suppression of Cu nucleation near the entrance of the trenches was achieved and then led to the superconformal gap filling of the nano-scale trenches. In the case for without hydrogen plasma treatments, however, over-grown Cu covered the whole entrance of nano-scale trenches. Detailed mechanism of nucleation suppression and resulting in nano-scale superconformal gap-filling of Cu will be discussed in detail.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.327-330
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• 2004

It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.