• 전자공학회논문지D
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• 제34D권8호
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• pp.35-40
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• 1997

To suppress the short channel effects in nMOSFET with 0.1.mu.m channel length, we have fabricated and characterized the ISRC n MOSFET with several process condition. When the recess oxide thickness is 100nm and the channel dose for threshold voltge adjustment is 6*10$^{12}$ /c $m^{-2}$ , B $F_{2}$$^{+}$, the maximum transconductance at $V_{DS}$ =2.0V is 455mS/mm and the BIDL is kept within 67mV. By comparing the ISRC n MOSFET with the conventioanl SHDD (shallowly heavily dopped drain) nMOSFET, we verify the suppression of short channel effects ISRC structure.e.

• 전자공학회논문지A
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• 제30A권8호
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• pp.63-71
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• 1993

To verify validity of the steady-state Nyquist theorem and the steady-state Nyquist theorem with hot carrier effects in semiconductor devices, we calculate thermal noise in n-i-n structures using both the steady-state Nyquist theorem and the Monte-Carlo method, and compare the results from these two-methods. When the carrier temperature is not far from the lattice temperature, the results from both methods agree with each other very well, but in the hot carrier regime there are some discrepancies. Our results support the argument that for MOSFETs and MESFETs operating in the linear region, the channel thermal noise should be explained by the steady-state Nyquist theorem rather than by the existing theories.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.240-250
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• 2010

Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an otherwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• 전자공학회논문지A
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• 제32A권6호
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• pp.82-90
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• 1995

We proposed SAW (Self-Algined Selectively Grown W-Gate) MOSFET structure, and strudied electrical characteristics of the fabricated SAW MOSFETs. The threshold volgate of 0.21${\mu}$m SAW NMOSFET was 0.18 V and that of 0.24 ${\mu}$m SAW PMOSFET was -0.16 V. The subthreshold slope was 74 mV/decade for NMOSFET and 82 mV/decade for PMOSFET. The maximum transconductance of NMOSFET and PMOSFET, at V$_{GS}$=2.5 V and V$_{DS}$=1.5 V, were260 mS/mm and 122 mS/mm. The measured saturation drain current at V$_{GS}$=V$_{DS}$ =2.5 V was 0.574 mA/${\mu}$m for NMOSFET and -0.228 mA/${\mu}$m for PMOSFET. The gate resistance of SAW MOSFET was about m$\Omega$cm and the n+-p junction capacitance of SAW MOSFET was about 10% lowas than that of the conventional MOSFET's.

• Transactions on Electrical and Electronic Materials
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• 제8권3호
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• pp.110-114
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• 2007

Dependence of the thermal stability of nickel silicide on the film stress of inter layer dielectric (ILD) layer has been investigated in this study and silicon nitride $(Si_3N_4)$ layer is used as an ILD layer. Nickel silicide was formed with a one-step rapid thermal process at $500^{\circ}C$ for 30 sec. $2000{\AA}$ thick $Si_3N_4$ layer was deposited using plasma enhanced chemical vapor deposition after the formation of Ni silicide and its stress was split from compressive stress to tensile stress by controlling the power of power sources. Stress level of each stress type was also split for thorough analysis. It is found that the thermal stability of nickel silicide strongly depends on the stress type as well as the stress level induced by the $Si_3N_4$ layer. In the case of high compressive stress, silicide agglomeration and its phase transformation from the low-resistivity nickel mono-silicide to the high-resistivity nickel di-silicide are retarded, and hence the thermal stability is obviously improved a lot. However, in the case of high tensile stress, the thermal stability shows the worst case among the stressed cases.

• 한국세라믹학회지
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• 제38권9호
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• pp.782-786
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• 2001

Cobalt silicide has been employed to Embedded DRAM (Dynamic Random Access Memory) and Logic (EDL) as contact material to improve its speed. We have investigated the influences of Ti and TiN capping layers on cobalt-silicided Complementary Metal-Oxide-Semiconductor (CMOS) device characteristics. TiN capping layer is shown to be superior to Ti capping layer with respect to high thermal stability and the current driving capability of pMOSFETs. Secondary Ion Mass Spectrometry (SIMS) showed that the Ti capping layer could not prevent the out-diffusion of boron dopants. The resulting operating current of MOS devices with Ti capping layer was degraded by more than 10%, compared with those with TiN.

• 대한전자공학회논문지
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• 제25권2호
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• pp.182-187
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• 1988

Hot carrier induced device degradation characteristics under DC bias stress have been investigated in n-MOSFETs with channel length of 1.2,1.8 um, and compared with those of LDD structure device with same channel length. Based on these results, the device lifetime in normal operating bias(Vgs=Vds=5V) is evaluated. The lifetimes of conventional and LDD n-MOSFET with channel length of 1.2 um are estimated about for 17 days and for 12 years, respectively. The degradation rate of LDD n-MOSFET under the same stress is the lowest at n-region implnatation dose of 2.5E15 cm-\ulcorner while the substrate current is the lowest at the dose of 1E13cm-\ulcorner Thses results show that the device degradation characteristics are basic measurement parameter to find optimum process conditions in LDD devices and evaluate a reliability of sub-micron device.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.46-52
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• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

• 한국재료학회지
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• 제18권5호
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• pp.272-276
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• 2008

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.