1 |
R. Venugopal, Z. Ren, S. Datta, M. S. Lundstrom,
and D. Jovanovic, “Simulating quantum transport
in nanoscale transistors: Real versus mode-space
approaches,” J. Appl. Phys., Vol.92, No.7,
pp.3730-3739, 2002.
DOI
ScienceOn
|
2 |
K. Natori, “Ballistic Metal-Oxide-Semiconductor
Field Effect Transistor,” J. Appl. Phys., Vol.76,
No.8, pp.4879-4890, 1994.
DOI
ScienceOn
|
3 |
Y. Taur, “Analytic solutions of charge and
capacitance in symmetric and asymmetric doublegate
MOSFETs,” IEEE Trans. Electron Devices,
Vol.48, No.12, pp.2861-2869, 2001.
DOI
ScienceOn
|
4 |
W. Y. Choi, H. Kim, B. Lee, J. D. Lee, and B. G.
Park, “Stable threshold voltage extraction using
Tikhonov’s regularization theory,” IEEE Trans.
Electron Devices, Vol.51, No.11, pp.1833-1839,
2004.
DOI
ScienceOn
|
5 |
X. Zhou, K. Y. Lim, and D. Lim, “A simple and
unambiguous definition of threshold voltage and its
implications in deep-submicron MOS device
modeling,” IEEE Trans. Electron Devices, Vol.46,
No.4, pp.807-809, 1999.
DOI
ScienceOn
|
6 |
D. J. Frank, R. H. Dennard, E. Nowak, P. M.
Solomon, Y. Taur, and H.- S. P. Wong, “Device
scaling limits of Si MOSFETs and their application
dependencies,” Proceedings of the IEEE, Vol.89,
pp.259-288, 2001.
DOI
ScienceOn
|
7 |
H. Tanno, M. Sakuraba, B. Tillack, and J. Murota,
“Heavy B atomiclayer doping characteristics in Si
epitaxial growth on B adsorbed Si(100) by
ultraclean low-pressure CVD system,”Solid-State
Electron., Vol.53, No.8, pp.877-879, 2009.
DOI
ScienceOn
|
8 |
S. Svizhenko, M. P. Anantram, T. R. Govindan, B.
Biegel, and R. Venugopal, “Two-dimensional
quantum mechanical modeling of nanotransistors,”
J. Appl. Phys., Vol.91, pp.2343-2354, 2002.
DOI
ScienceOn
|
9 |
J. Murota, M. Sakuraba, and B. Tillack,
“Atomically controlled processing for Group IV
semiconductors by chemical vapor deposition,” Jpn.
J. Appl. Phys., Vol.45, No.9, pp.6767-6785, 2006.
DOI
|
10 |
B. Tillack, Y. Yamamoto, D. Bolze, B. Heinemann,
H. Rucker, D. Knoll, J. Murota, and W. Mehr,
“Atomic layer processing for doping of SiGe,”
Thin Solid Films, Vol.508, No.1, pp.279-283, 2006.
DOI
ScienceOn
|
11 |
G. Curatola, G. Fiori, and G. Iannaccone,
“Modelling and simulation challenges for
nanoscale MOSFETs in the ballistic limit,” Solid-State Electron., Vol.48, No.4, pp.581-587, 2006.
DOI
ScienceOn
|
12 |
D. Munteanu and J. L. Autran, “Two-dimensional
modeling of quantum ballistic transport in ultimate
double-gate SOI devices,” Solid-State Electron.,
Vol.47, No.7, pp.1219-1225, 2003.
DOI
ScienceOn
|
13 |
S. Datta, “Nanoscale device modeling: the Greens
function method,” Superlattices Microstruct.,
Vol.28, No.4, pp.253-278, 2000.
DOI
ScienceOn
|
14 |
A. Rahman, J. Guo, S. Datta, and M. S. Lundstrom,
“Theory of ballistic nanotransistors,” IEEE Trans.
Electron devices, Vol.50, No.9, pp.1853-1864,
2003.
DOI
ScienceOn
|
15 |
H. Zhong, S.-N. Hong, Y.-S. Suh, H. Lazar, G.
Heuss, and V. Misra, “Properties of Ru-Ta alloys
as gate electrodes for NMOS and PMOS silicon
devices,” IEDM Tech. Dig., pp.467-470, 2001.
|
16 |
T.-L. Li, C.-H. Hu, W.-L. Ho, H. C. H. Wang, and
C.-Y. Chang, “Continuous and precise work
function adjustment for integratable dual metal gate
CMOS technology using Hf-Mo binary alloys,”
IEEE Trans. Electron Devices, Vol.52, No.6,
pp.1172-1179, 2005.
DOI
ScienceOn
|
17 |
J. K. Schaeffer, C. Capasso, L. R. C. Fonseca, S.
Samavedam, D. C. Gilmer, and Y. Liang,
“Challenges for the integration of metal gate
electrodes,” IEDM Tech. Dig., pp.287-290, 2004.
|
18 |
V. Misra, H. Zhong, and H. Lazar, “Electrical
properties of Ru-based alloy gate electrodes for
dual metal gate Si-CMOS,” IEEE Electron. Device
Lett., Vol.23, No.6, p.354356, 2002.
DOI
ScienceOn
|
19 |
X. P. Wang, M.-F. Li, C. Ren, X. F. Yu, C. Shen,
H. H. Ma, A. Chin, C. X. Zhu, J. Ning, M. B. Yu,
and D.-L. Kwong, “Tuning effective metal gate
work function by a novel gate dielectric HfLaO for
nMOSFETs,” IEEE Electron. Device Lett., Vol.27,
No.1, pp.31-33, 2006.
DOI
ScienceOn
|
20 |
C.-H. Lu, G. M. T. Wong, M. D. Deal, W. Tsai, P.
Majhi, C. O. Chui, M. R. Visokay, J. J. Chambers,
L. Colombo, B. M. Clemens, and Y. Nishi,
“Characteristics and mechanism of tunable work
function gate electrodes using a bilayer metal
structure on ,” IEEE Electron.
Device Lett., Vol.26, No.7, pp.445-447, 2005.
DOI
ScienceOn
|
21 |
H. Lu, W. Y. Lu, and Y. Taur, “Effect of body
doping on double-gate MOSFET characteristics,”
Semicond. Sci. Technol., Vol.23, No.1, 2008.
|
22 |
J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M.
Doczy, B. Jin, D. Lionberger, M. Metz, W.
Rachmady, M. Radosavljevic, U. Shah, N. Zelick,
and R. Chau, “Tri-Gate transistor architecture with
High gate dielectrics, Metal gates and Strain
engineering,” in Symp. on VLSI Technology, 2006,
pp.50-51.
|
23 |
Y. Taur, C. H. Wann, and D. J. Frank, “25 nm
CMOS design considerations,” IEDM Tech. Dig.,
pp.789-792, 1998.
|
24 |
A. Asenov, A. R. Brown, J. H. Davies, S. Kaya,
and G. Slavcheva, “Simulation of intrinsic
parameter fluctuations in decananometer and
nanometer-scale MOSFETs,” IEEE Trans.
Electron Devices, Vol.50, No.9, pp.1837-1852,
2003.
DOI
ScienceOn
|
25 |
R. Lin, Q. Lu, P. Ranade, T.-J. King, and C. Hu,
“An djustable work function technology using Mo
gate for CMOS devices,” IEEE Electron. Device
Lett., Vol.23, No.1, pp.49-51, 2002.
DOI
ScienceOn
|
26 |
G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy,
and A. Asenov, “Simulation study of individual
and combined sources of intrinsic parameter
fluctuations in conventional nano-MOSFETs,”
IEEE Trans. Electron Devices, Vol.53, No.12,
pp.3063-3070, 2006.
DOI
ScienceOn
|
27 |
M. Ieong, H.-S. P. Wong, E. Nowak, J. Kedzierski,
and E. C. Jones, “High performance double-gate
device technology challenges and opportunities,” in
Procedings of International Symposium on Quality
Electronic Design, 2002, pp.492-495.
|
28 |
F. Liu, L. Zhang, J. Zhang, J. He, and M. Chan,
“Effects of body doping on threshold voltage and
channel potential of symmetric DG MOSFETs with
continuous solution from accumulation to stronginversion
regions,” Semicond. Sci. Technol., Vol.24,
No.8, p. 085005(8pp), 2009.
|
29 |
C. Y. Lin, M. W. Ma, A. Chin, Y. C. Yeo, C. Zhu,
M. F. Li, and D.-L. Kwong, “Fully silicided NiSi
gate on MOSFETs,” IEEE Electron. Device
Lett., Vol.24, No.5, pp.348-350, 2003.
DOI
ScienceOn
|
30 |
J. Liu, H. C. Wen, J. P. Lu, and D.-L. Kwong,
“Dual-work-function metal gates by full
silicidation of poly-Si with Co-Ni bi-Layers,” IEEE
Electron. Device Lett., Vol.26, No.4, pp.228-230,
2005.
DOI
ScienceOn
|
31 |
D. S. Yu, C. H. Wu, C. H. Huang, A. Chin, W. J.
Chen, C. Zhu, M. F. Li, and D.-L. Kwong, “Fully
Silicided NiSi and Germanided NiGe dual gates on
n- and p-MOSFETs,” IEEE Electron. Device
Lett., Vol.24, No.11, pp.739-741, 2003.
DOI
ScienceOn
|
32 |
A. Asenov, “Random dopant induced threshold
voltage lowering and fluctuations in Sub-0.1
MOSFETs: A 3-D atomistic simulation study,”
IEEE Trans. Electron Devices, Vol.45, pp.2505-2513, 1998.
DOI
ScienceOn
|
33 |
K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y.
Arimoto, “Scaling theory for Double-Gate SOI
MOSFETs,” IEEE Trans. Electron Devices, Vol.40,
No.12, pp.2326-2329, 1993.
DOI
ScienceOn
|
34 |
R. W. Keyes, “The effect of randomness in the
distribution of impurity atoms on FET thresholds,”
Appl. Phys. A, Vol.8, No.3, pp.251-259, 1975.
DOI
|
35 |
R. W. Keyes, “Effect of randomness in the
distribution of impurity ions on FET thresholds in
integrated electronics,” IEEE J. Solid-State
Circuits, Vol.10, No.4, pp.245-247, 1975.
DOI
|
36 |
A. Asenov, “Random dopant induced threshold
voltage lowering and fluctuations in sub 50 nm
MOSFETs: a statistical 3D ‘atomistic’ simulation
study,” Nanotechnology, Vol.10, pp.153-158, 1999.
DOI
ScienceOn
|
37 |
A. Asenov and S. Saini, “Polysilicon gate
enhancement of the random dopant induced
threshold voltage fluctuations in sub-100 nm
MOSFETs with ultrathin gate oxide,” IEEE Trans.
Electron Devices, Vol.47, pp.805-812, 2000.
DOI
ScienceOn
|
38 |
A. R. Brown, A. Asenov, and J. R. Watling,
“Intrinsic fluctuations in sub 10-nm Double-Gate
MOSFETs introduced by discreteness of charge
and matter,” IEEE Trans. Nanotechnology, Vol.1,
No.4, pp.195-200, 2002.
DOI
ScienceOn
|
39 |
A. Asenov, S. Kaya, and A. R. Brown, “Intrinsic
parameter fluctuations in decananometer
MOSFETs introduced by gate line edge
roughness,” IEEE Trans. Electron Devices, Vol.50,
No.5, pp.1254-1260, 2003.
DOI
ScienceOn
|