• Transactions of the Korean Society of Mechanical Engineers
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• v.15 no.2
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• pp.544-556
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• 1991

The optimization of many engineering design problems requires a nonlinear programming algorithm that is robust and efficient. A general-purpose nonlinear optimization program IDOL (Interactive Design Optimization Library) is developed based on the Augmented Lagrange Mulitiplier (ALM) method. The ideas of selecting a good initial design point, using resonable initial values for Lagrange multipliers, constraints scaling, descent vector restarting, and dynamic stopping criterion are employed for computational enhancement to the ALM method. A descent vector is determined by using the Broydon-Fletcher-Goldfarb-Shanno (BFGS) method. For line search, the Incremental-Search method is first used to find bounds on the solution, then the bounds are reduced by the Golden Section method, and finally a cubic polynomial approximation technique is applied to locate the next design point. Seven typical test problems are solved to show IDOL efficient and robust.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.5
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• pp.17-30
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• 2001

In this paper, we implemented a scalar multiplier needed at an elliptic curve cryptosystem over standard basis in $GF(2^{163})$. The scalar multiplier consists of a radix-16 finite field serial multiplier and a finite field inverter with some control logics. The main contribution is to develop a new fast finite field inverter, which made it possible to avoid time consuming iterations of finite field multiplication. We used an algorithmic transformation technique to obtain a data-independent computational structure of the Extended Euclid GCD algorithm. The finite field multiplier and inverter shown in this paper have regular structure so that they can be easily extended to larger word size. Moreover they can achieve 100% throughput using the pipelining. Our new scalar multiplier is synthesized using Hyundai Electronics 0.6$\mu\textrm{m}$ CMOS library, and maximum operating frequency is estimated about 140MHz. The resulting data processing performance is 64Kbps, that is it takes 2.53ms to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption & decryption and key exchange in real time embedded-processor environments.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.899-902
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• 1999

In this paper, we designed a equalizer that moved the multipath of channel in 8-VSB transmission receiver. After doing the initial equalization with "LMS(Least Mean Square)"aigorithm. this equalizer used "Stop-and-Go" algorithm. Because of estimating SER(Symbol to Error Ratio) every a training sequence, this can positively cope with transformation of channel and because of using fast clock than symbol-clock(10.76 MHz), we are able to reduce a multiplier.

• Journal of KSNVE
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• v.6 no.6
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• pp.771-779
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• 1996

In this paper, double Fourier sine series is used as a modal displacement functions of a rectangular plate and applied to the free vibration analysis of a rectangular plate under various boundary conditions. The method of stationary potential energy is used to obtain the modal displacements of a plate. To enhance the flexibility of the double Fourier sine series, Lagrangian multipliers are utilized to match the geometric boundary conditions, and Stokes' transformation is used to handle the displacements that are not satisfied by the double Fourier sine series. The frequency parameters and mode shapes obtained by the present method are compared with those obtained by MSC/NASTRAN and other analysis.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.1
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• pp.41-47
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• 2008

This paper presents a new digit level LSB-first multiplier for computing a modular multiplication and a modular squaring simultaneously over finite field GF($2^m$). To derive $L{\times}L$ digit level architecture when digit size is set to L, the previous algorithm is used and index transformation and merging the cell of the architecture are proposed. The proposed architecture can be utilized for the basic architecture for the crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity, and concurrency.

• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.245-247
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• 1992

We utilize as a processor TMS320C25 (Texas Instrument) in making a driver for a 4 pole PM synchronous servo motor. TMS320C25 has a 32bit ALU and a 16 bit hardware multiplier, and the maximum instruction execution rate is 10MIPS at 40MHz. We adopted a space vector modulation PWM method. An interesting point of this work is that PWM wave is generated by utilizing timer interrupts. Hence, in the rest of time the processor can take care of the other routine such as Park's coordinate transformation and the computation required in the feedback loops. Thus, it mates the hardware circuit very simple. Due to the decrease in the number of components, the motor drive system becomes more fault-tolerant and cost-optimized. Also, more flexibility is gained in changing the control parameters.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.1
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• pp.12-23
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• 1994

This paper proposes an optimal design software for the open-chain dynamic systems whose governing equations are expressed as differential equation. In this software, an input module and an automatic creation module of the equation of motion are developed to contrive the user's convenience. To analyze the equation of motion of the dynamic systems, variable-order and variable-stepsize Adams-Bashforth-Moulton predictor-corrector method is used to improve the efficiency. For the optimization and the design sensitivity analysis, ALM(augmented lagrange multiplier)method and adjoint variable method are adopted respectively. An output module with which the user can compare and investigate the analysis and the optimization results through tables and graphs is also provided. The developed software is applied to three typical dynamic response optimization problems, and the results compare very well with those available in the literature, demonstrating its effectiveness.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.22 no.1
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• pp.52-64
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• 2023

This paper concentrated on estimating the travel time value of individual regional bus passengers in various in-vehicle crowding conditions. In the analysis model, the traffic-selection data of individual transportation passengers based on smart-card data were used. Variables which reflect the level of in-vehicle crowding and the variables of in-vehicle travel time that reflect the level of in-vehicle crowding were included in the model using Box-Cox transformation. The result of this paper indicates that the travel time value experienced by individual users would increase as the in-vehicle crowding level increases. The smart card data used in this paper is considered to have significant implications in terms of conducting more sophisticated and realistic qualitative research to reflect the values of variables for in-vehicle traffic hours and in-vehicle crowding levels, which previously had limitations in observation and quantification. It is expected that the effects of improvement measures for reducing congestion on regional buses can be considered quantitatively by applying the estimation results of crowding multiplier.

• ETRI Journal
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• v.30 no.6
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• pp.826-832
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• 2008

The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.5
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• pp.1138-1149
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• 1993

A new mode synthesis method using Lagrange multipliers and substructure hybrid interface modes is presented. Substruture governing equations of motion are derived using Lagrange equations and the constraints of geometric compatibility between the substructures are treated with Lagrange multipliers. Fixed, free, and loaded interface modes can be employed for the modal bases of each substructure. In cases of the fixed and loaded interface modes, two successive modal transformation relations are used. Compared with the conventional mode synthesis methods, the suggested method does not construct the equations of motion of the coupled structure and the final characteristic equation becomes a polynomial. Only modal parameters of each substructure and geometric compatibility conditions are needed. The suggested method is applied to a simple lumped mass model and parametric study is performed.