• 대한전기학회논문지:전력기술부문A
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• 제48권10호
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• pp.1317-1326
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• 1999

As the integration ratio and operation speed increase, it has become an important problem to estimate the dissipated power during the design procedure as a method to reduce the TTM(time to market). This paper proposed a prediction model to estimate the maximum dissipated power of a CMOS logic gate. This model uses a calculational method. It was formed by including the characteristics of MOSFETs of which a CMOS gate consists, the operational characteristics of the gate, and the characteristics of the input signals. As the modeling process, a maximum power estimation model for CMOS inverter was formed first, and then a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. For experiment, several CMOS gates were designed in layout level by $0.6{\mu}m$ layout design rule. The result by comparing the calculated results with those from HSPICE simulations for the gates showed that the gate conversion model has within 5% of the relative error rate to the SPICE and the maximum power estimation model has within 10% of the relative error rate. Thus, the proposed models have sufficient accuracies. Also in calculation time, the proposed models was more than 30 times faster than SPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• 한국정보통신학회논문지
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• 제17권1호
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• pp.151-157
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• 2013

본 연구에서는 다중게이트 구조인 나노 와이어 n-채널 무접합(junctionless)와 반전모드(inversion mode) 다중게이트 MOSFET(Multiple-Gate MOSFET : MuGFET)의 PBTI에 의한 소자 특성 저하를 비교 분석하였다. PBTI에 의해서 무접합 및 반전모드 소자의 문턱전압이 증가하는 것으로 관측되었으며 무접합 소자의 문턱전압 변화가 반전모드 소자보다 작음을 알 수 있었다. 그러나 소자특성 저하 비율은 반전모드 소자가 무접합 소자보다 큰 것으로 관측되었다. 특성저하 활성화 에너지는 반전모드 소자가 무접합 소자보다 큰 것을 알 수 있었다. PBTI에 의한 소자 특성 저하가 무접합 소자보다 반전모드 소자가 더 심한 것을 분석하기 위하여 3차원 소자 시뮬레이션을 수행하였다. 같은 게이트 전압에서 전자의 농도는 같으나 수직방향의 전계는 반전모드 소자가 무접합 소자보다 큰 것을 알 수 있었다.

• Ecology and Resilient Infrastructure
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• 제5권4호
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• pp.276-284
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• 2018

하단배출 형태의 연직수문을 대상으로 퇴적토 배출특성에 따른 두부침식 거리비, 퇴적토 이동거리와 이동량을 분석하기 위해 수리 모형실험과 차원해석을 수행하였다. Froude 수와 배출특성의 상관관계를 도식화하고, 퇴적토 배출특성을 지배하는 무차원 매개변수에 의한 다중회귀식을 제안하였다. 두부침식거리, 퇴적토 이동거리와 이동량에 대한 각 다중회귀 분석식의 결정계수는 각각 0.618, 0.632, 0.866으로 높게 나타났다. 개발한 퇴적토 배출특성식의 사용성을 평가하기 위해 실제 측정값과 회귀분석식에 의해 계산된 값의 95%의 예측 신뢰구간 분석을 수행하였고, 두부침식거리, 퇴적토 이동거리와 이동량에 대한 예측의 정확도 분석차원의 NSE (Nash-Sutcliffe Efficiency), RMSE (root mean square)와 MAPE (mean absolute percentage error)는 적절한 것으로 판단되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.859-862
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• 2003

This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.148-150
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• 2009

We have developed 15 inch, 130 blocks local dimming FEL using printed CNT emitters, in which multiple FE blocks were built with a common gate electrode. Cathode electrode formed by the double-metal technique, in which an insulator is interposed between the addressing bus and cathode electrode.

• 정보처리학회논문지A
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• 제11A권2호
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• pp.115-122
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• 2004

본 논문에서는 전류모드 CMOS를 사용하여 다치 가산기 및 다치 승산기를 구현하였으며, 먼저 효과적인 집적회로 설계 이용성을 갖는 전류모드 CMOS를 사용하여 3치 T-게이트와 4치 T-게이트를 구현하였다. 구현된 다치 T-게이트를 조합하여 유한체 $GF(3^2)$의 2변수 3치 가산표와 승산표를 실현하는 회로를 구현하였으며, 이들 다치 T-게이트를 사용하여 유한체 $GF(4^2)$의 2변수 4치 가산표와 승산표를 실현하는 회로를 구현하였다. 또한, Spice 시뮬레이션을 통하여 이 회로들에 대한 동자특성을 보였다. 다치 가산기 및 승산기들은 $1.5\mutextrm{m}$ CMOS 표준 기술의 MOSFET 모델 LEVEL 3을 사용하였고, 단위전류는 $15\mutextrm{A}$로 하였으며, 전원전압은 3.3V를 사용하였다. 본 논문에서 구현한 전류모드 CMOS의 3치 가산기와 승산기, 4치 가산기와 승산기는 일정한 회선경로 선택의 규칙성, 간단성, 셀 배열에 의한 모듈성의 이점을 가지며 특히 차수 m이 증가하는 유한체의 두 다항식의 가산 및 승산에서 확장성을 가지므로 VLSI화 실현에 적합한 것으로 생각된다.

• Transactions on Electrical and Electronic Materials
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• 제10권2호
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• pp.35-39
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• 2009

A novel Helmholtz coil inductively coupled plasma(H-ICP) etcher is proposed and characterized for deep nano-scale CMOS technology. Various hardware tests are performed while varying key parameters such as distance between the top and bottom coils, the distance between the chamber ceiling and the wafer, and the chamber height in order to determine the optimal design of the chamber and optimal process conditions. The uniformity was significantly improved by applying the optimum conditions. The plasma density obtained with the H-ICP source was about $5{\times}10^{11}/cm^3$, and the electron temperature was about 2-3 eV. The etching selectivity for the poly-silicon gate versus the ultra-thin gate oxide was 482:1 at 10 sccm of $HeO_2$. The proposed H-ICP was successfully applied to form multiple 60-nm poly-silicon gate layers.

• 한국실내디자인학회논문집
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• 제17권5호
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• pp.72-79
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• 2008

Nagaya is one of the traditional Japanese housing types in which multiple houses are attached together. In Nagaya, walls are shared by several houses but entrances are privately owned by houses. Nagaya consists of many wooden houses for common people located in parallel with narrow alleys between them. Nagaya was one of the representative housing types in Japanese architectural history. This research is to study the background of the origination of Nagaya in Japan, the characteristics of space and land planning, the features and causes of the changes in the space and land planning. In this research, we observed and analyzed unit plans of a block of gate-type Nagayas in Hanan, Osaka. The results are as follows. First, as the inner alleys(Roji) are closed, the number of entrances to each housing lot decreased from two to one since one entrance that used to be open to inner alleys(Roji) are permanently closed. Second, walls between streets and housing lots which used to be one of the outstanding characteristics of gate-type Nagayas are disappearing. Third, as the bathrooms are added to houses, the front gardens are being degraded to empty spaces or sometimes totally removed. Fourth, the space in the first floor of houses become family spaces, and that in the second floor is divided into private rooms for individuals.

• 대한산업공학회지
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• 제29권2호
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• 대한토목학회논문집
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• 제5권1호
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• pp.91-100
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• 1985

본(本) 연구(硏究)는 한강유역(漢江流域) 댐군(群)의 비상사태하(非常事態下)(큰 홍수파(洪水波) 유하시(流下時))에서의 수문조작(水門操作) 기준설정(基準設定)에 관한 것으로 얻어진 결과(結果)는 다음과 같다. 1) 수문조작(水門操作)을 저수위(貯水位)와 유입량(流入量)으로 실시(實施)할 수 있게끔 6개 댐(화천(華川), 춘천(春川), 소양강(昭陽江), 의암(衣岩), 청평(淸平), 인당(人堂)댐)에 대해 수문조작(水門操作) 기준(基準)을 수식화(數式化)하였다. 2) 수문(水門)의 개방면적(開放面積), 유입량(流入量), 저수위(貯水位), 방류량(放流量) 간의 다중회귀분석(多重回歸分析)에 의해서 얻어진 식(式)으로 홍수추적(洪水追跡)을 실시한 결과 그 적용가능성(適用可能性)을 확인(確認)하였다. 3) 본(本) 연구(硏究)에서 얻어진 수문조작(水門操作) 기준(基準)과 홍수추적방법(洪水追跡方法)을 사용(使用)하여 비상사태하(非常事態下)(큰 홍수파(洪水波) 유하시(流下時))에서의 각 댐을 검토(檢討)한 바, 모두 안전(安全)하였으나, 소양강(昭陽江), 의암(衣岩), 청평(淸平)댐만은 저수지(貯水池) 초기방류수위(初期放流水位)를 미리 저하(低下)시킨 상태(狀態)에서 수문조작(水門操作)이 이루어져야 할 것이다.