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Statistical Design of Experiments and Analysis: Hierarchical Variance Components and Wafer-Level Uniformity on Gate Poly-Silicon Critical Dimension  

Park, Sung-min (System LSI, Samsung Electronics Co., Ltd)
Kim, Byeong-yun (System LSI, Samsung Electronics Co., Ltd)
Lee, Jeong-in (System LSI, Samsung Electronics Co., Ltd)
Publication Information
Journal of Korean Institute of Industrial Engineers / v.29, no.2, 2003 , pp. 179-189 More about this Journal
Abstract
Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.
Keywords
design of experiments; variance components; uniformity test; critical dimension; semiconductor;
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