• Journal of the Korea Society of Computer and Information
• /
• v.16 no.5
• /
• pp.1-11
• /
• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.

• Journal of the Institute of Convergence Signal Processing
• /
• v.9 no.3
• /
• pp.213-218
• /
• 2008

This paper describes hardware-based high speed multimedia data reassembly processor for remote multimedia Set-Top-Box(MSTB) of interactive satellite multimedia communication system. The conventional multimedia data reassembly scheme is based on software processing of MSTB. As increasing of transmission rate for multimedia data services, the CPU load of remote MSTB is increased and reassembly performance of MSTB is limited. To provide high speed multimedia data service to end user, we proposed hardware based high speed multimedia data reassembly processor. It is implemented by using an FPGA, a PCI interface chip, and RAMs. And it is integrated in MSTB and tested. It has been confirmed to meet required all functions and processing rate up to 116Mbps.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.11A
• /
• pp.1117-1123
• /
• 2008

Applications for mobile multimedia are testing the performance limits of present day CPUs with variety. However, hardwired solutions are inflexible and expensive to develop. CPUs with flexibility have limitation of performance. So, the requirement for both ASIC-like performance and CPU-like flexibility has led to reconfigurable processor. Mobile systems require low power and high performance concurrently. In this paper, we propose reconfigurable processor for mobile multimedia with high energy efficiency. Reconfigurable processor with 121MOPS/mW is developed by 130nm CMOS technology. And the processor was simulated for energy efficiency with 539MOPS/mW by 90nm CMOS technology and effective use of instructions. And we tested its applications for multimedia field. We tested the case of inverse MDCT for MP3 and DF for MPEG4 and ME for H.264.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.97-100
• /
• 2001

A 3-way VLIW multimedia signal processor capable of efficient repeated operations as well as both load/store and type transformations for various data types is presented. It is composed of a 32-bit execution unit that can execute two instructions in parallel, an independent load/store unit and a control unit. The processor is implemented with 0.6${\mu}{\textrm}{m}$ gate array and the results are discussed.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.42 no.1
• /
• pp.95-100
• /
• 2005

This paper proposes a DVS method which effectively reduces the power consumption of multimedia signal processor. Analytic derivations of effective range of its power saving factor are obtained with the assumption of a Gaussian distribution for the frame-based computational burden of the multimedia processor. A closed form equation of the power saving factor is derived in terms of the mean-standard deviation of the distribution. An MPEG-2 video decoder algorithm and AAC encoder algorithm are tested on ARM9 RISC processor for the experimental verification of the power saying of the proposed DVS approach. The experimental results with diverse MPEG-2 video and audio files show 50～30% power saving factor and show good agreement with those of the analytically derived values.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.155-158
• /
• 2005

An invesitigation on power consumption of a mobile multimedia system using OFDM and MDVS technique is reported here. Analysis and simulation are performed to find the significances of proposed Microscopic Dynamic Voltage Scaling(MDVS) tehnique[4] on digital processor in terms of power saving. A study is also made to show power reduction in mobile multimedia system by incorporating OFDM modulation scheme in RF front-end. Finally, overall power consumption by functionally distinguished blocks ie. RF front-end, digital processor and human interface unit is shown here. Total power consumption is 8.2W for 2Mbps SD-quality WCDMA multimedia video service - the power consumption of digital processor is 3.9W(48%), the power consumption of RF front-end is 3.2W (36%), and the power consumption of interface is 1.8W(16%). Power saving of applying purposed MDVS technique is 35% in digital processor, and power saving of OFDM technique is 10-12dB in RF front-end.

• Journal of Korea Multimedia Society
• /
• v.9 no.8
• /
• pp.963-970
• /
• 2006

In this paper, we proposed a motion picture processor for using low-cost color super twisted nematic liquid crystal display(CSTN-LCD). The proposed processor apply a new driving scheme using SFP(Subgroup Frame Pattern), so we extends gray scale and eliminates flicker phenomenon. In addition, we apply the BFI (Black Field Insertion) to the design compensated for response time of a LC (Liquid Crystal). We use an edge enhancement and interpolation method to improve image quality of motion picture. The hardware architecture of proposed processor has been implemented and verified on a prototype FPGA board. The proposed method can be used in the display devices such as PDA(Personal Digital Assistants), mobile phone, and PMP(Portable Multimedia Player).

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.6
• /
• pp.420-435
• /
• 2001

As multimedia technology has rapidly grown recently, many researches to process multimedia data efficiently using general-purpose processors have been studied. In this paper, we proposed multimedia instructions which can process multimedia data effectively, and suggested a processor architecture for those instructions. The processor was described with Verilog-HDL in the behavioral level and simulated with CADENCE$^{TM}$ tool. Proposed multimedia instructions are total 48 instructions which can be classified into 7 groups. Multimedia data have 64-bit format and are processed as parallel subwords of 8-bit 8 bytes, 16-bit 4 half words or 32-bit 2 words. Modeled processor is developed based on the Integer Unit of SPARC V.9. It has five-stage pipeline RISC architecture with Harvard principle.e.

• IE interfaces
• /
• v.17 no.4
• /
• pp.466-471
• /
• 2004

In this paper, I develop a simple dynamic resource allocation algorithm that reduces the call blocking rate by improving the resource utilization of the WCDMA (Wideband Code Division Multiple Access) systems under multimedia service environment. Simulation results show that the proposed algorithm significantly reduces the blocking rate of high speed multimedia calls. The algorithm developed in this paper is currently working in the commercial WCDMA IMT-2000 system.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.931-934
• /
• 1999

For applications in multimedia to which genuine RISC microprocessors are not suitably applicable, a new generation of fast and flexible microprocessors is required. In this paper, as a technique of integrating DSP functionality in a general RISC processor, a RISC that can execute DSP extension instructions is developed to improve the performance of multimedia application execution. This processor can execute DSP instructions in parallel with the execution of ALU instructions for efficient and fast execution. In addition, the execution ability of integer instructions is improved by enhancing the RISC core itself.