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http://dx.doi.org/10.9708/jksci.2011.16.5.001

Hardware Design and Implementation of a Parallel Processor for High-Performance Multimedia Processing  

Kim, Yong-Min (School of Electrical Engineering, University of Ulsan)
Hwang, Chul-Hee (School of Electrical Engineering, University of Ulsan)
Kim, Cheol-Hong (Department of Electronics and Computer Engineering, Chonnam National University)
Kim, Jong-Myon (School of Electrical Engineering, University of Ulsan)
Publication Information
Journal of the Korea Society of Computer and Information / v.16, no.5, 2011 , pp. 1-11 More about this Journal
Abstract
As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.
Keywords
Parallel processor; multimedia processing; pipeline architecture; hardware design;
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1 M.-K. You, Y.-J. Oh, G.-Y. Song, "System-level hardware function verification system," Journal of The Institute of Signal Processing and Systems," vol. 11, no. 2, pp. 86-91, April 2010.
2 Xilinx Userguide: http://www.xilinx.com/support/doucumentation.user_guides/ug070.pdf
3 J. C. Eble, V. K. De, D. S. Wills, J. D. Meindl, "Generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001," Proceedings of the Ninth Annual IEEE International ASIC Conference, pp. 193-196, September 1996.
4 Jongmyon Kim, Yong-Min Kim, Cheol-Hong Kim, "Performance evaluation of multimedia extensions on variable many-core processors," in the International Conference on Computer Design (CDES'10), pp. 98-104, July 2010.
5 "Connection machine model CM-2 technical summary," Thinking Machines Corp., version 51, May 1989.
6 TMS320C64x families: http://www.bdti.com/procsum /tic64xx.htm.
7 M. J. Irwin, R. M. Owens, "A two-dimensional, distributed logic processor," IEEE Trans. on Computers, vol. 40, no. 10, pp. 1094-1101, 1991.   DOI   ScienceOn
8 M. Bolotski, R. Armithrajah, W. Chen, "ABACUS: A high performance architecture for vision," in Proceedings of the International Conference on Pattern Recognition, 1994.
9 S. M. Chai, T. Taha, D. S. Wills, J. D. Meindl, "Heterogeneous architecture models for interconnect-motivated system design," IEEE Trans. on VLSI Systems, vol. 8, no. 6, pp. 660-670, 2000.   DOI   ScienceOn
10 L. W. Tucker and G. G. Robertson, "Architecture and applications of the connection machine," IEEE Computer, vol. 21, no. 8, pp. 26-38, 1988.
11 MarPar (MP-2) System Data Sheet. MarPar Corporation, 1993.
12 A. Krikelis, I. P. Jalowiecki, D. Bean, R. Bishop, M. Facey, D. Boughton, S. Murphy, and M. Whitaker, "A programmable processor with 4096 processing units for media applications," in Proc. of the IEEE Intl. Conf. on Acoustics, Speech, and Signal Processing, vol. 2, pp. 937-940, May. 2001.
13 A. Shahbahrami, B. Juurlink, and S. Vassiliadis, "Versatility of extended subwords and the matrix register file," ACM Transactions on Architecture and Code Optimization (TACO), vol. 5, no. 1, Article 5:1-5:30, 2008.
14 J.-C. Chiu, Y.-L. Chou, and H.-Y. Tzeng, "A Multi-streaming SIMD Architecture for Multimedia Applications", in Proceedings of the 6th ACM conference on Computing frontiers, pp. 51-60, 2009.
15 A. Gentile and D. S. Wills, "Portable video supercomputing," IEEE Trans. on Computers, vol. 53, no. 8, pp. 960-973, Aug. 2004.   DOI   ScienceOn
16 S.H. Lee, "The design and implementation of parallel processing system using Nios(R) II embedded processor", Journal of the Korea Society of Computer and Information, vol. 14, no. 1, pp. 97-103, Nov. 2009.
17 P. Ranganathan, S. Adve, and N. P. Jouppi, "Performance of image and video processing with general-purpose processors and media ISA extensions," in Proc. of the 26th Intl. Sym. on Computer Architecture, pp. 124-135, May. 1999.
18 R. Bhargava, L. John, B. Evans, and R. Radhakrishnan, "Evaluating MMX technology using DSP and multimedia applications," in Proc. of IEEE/ACM Sym. on Microarchitecture, pp. 37-46, 1998.
19 N. Slingerland and A. J. Smith, "Measuring the performance of multimedia instruction sets," IEEE Trans. on Computers, vol. 51, no. 11, pp. 1317-1332, Nov. 2002.   DOI   ScienceOn
20 M.K. Chung, S.M. Park, and N.W. Eum, "Technology and trend of parallel processor," Electronics and Telecommunications Trends, vol. 24, no. 6, pp. 86-93, Dec. 2009.
21 J.J. Lee, S.M. Park, and N.W. Eum, "Application specific instruction set processor for multimedia applications," Electronics and Telecommunications Trends, vol. 24, no. 6, pp. 94-98, Dec. 2009.
22 S.H. Kim, S.B. Nam, and H.J. Lim, "An improved area edge detection for real-time image processing," Journal of the Korea Society of Computer and Information, vol. 14, no. 1, pp. 99-106, Jan. 2009.