• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.960-964
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• 2003

In this paper, the CMOS integrated circuit technique for implementing current-mode maximum and minimum operations scheme is described. The maximum and minimum operations are incorporated into the same scheme with parallel processing. Using this scheme as the basic unit, an analog three-input maximum, median, and minimum circuit is designed. The performance of the proposed circuit shows a very sharp transfer characteristic and high accuracy. The proposed circuit achieves a high-speed operation, which is suitable for real-time systems. The PSPICE simulation results demonstrating the characteristic of the proposed circuit are included.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.69-72
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• 2003

This paper presents a current-mode multiple-input minimum circuit. The proposed circuit can be implemented by applying De Morgan’s law. The circuit diagram is simple and modular. It operates using a single 2.5V supply and has very low dissipation. The realization method is suitable for fabrication using CMOS technology and all transistors are operated in their saturation region. The performances of this proposed circuit were studied using the PSPICE analog simulation program. The simulation results show the approval of this circuit that it has adequate basic performances for a real-time fuzzy controller and a fuzzy computer.

• Journal of the Korean Society of Safety
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• v.25 no.5
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• pp.22-26
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• 2010

The ignitability(minimum ignition energy, MIE) of a suspended dust clouds is very important aspect of technical safety indices. This paper reported the experimental results dealing with the influence of discharge circuit on the MIE of a suspended dust clouds. The movement of a suspended dust clouds was also observed with the high speed camera. The Hartmann vertical-tube apparatus(MIKE-3) described in the international standard of IEC and Polypropylene (PP, 50% volume-average, D50: $761{\mu}m$) resin powders were used in this experiment. The following results were obtained: (1) the MIE of a suspended PP powder depended markedly on the discharge circuit; in other words, when a resistor was connected in series with the discharge sparking circuit(RC), the lowest value(31mJ) of MIE was obtained for a suspended PP powder comparison with the other circuits(C circuit; 370mJ or LC circuit; 71mJ). (2) the discharge duration time is more important than other factors with regard to MIE of a suspended PP powder.

• Journal of Advanced Navigation Technology
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• v.3 no.2
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• pp.174-184
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• 1999

In this paper, the equations which can be used to calculate the minimum series stabilizing resistance and /or the minimum parallel stabilizing conductance using the S parameters of an active device has been derived. The equation derived can be used to design a stabilizing circuit of minimum loss of a maximum available gain of a device when the circuit is adopted. For the case of KGF1254B which can be used at 1.9 GHz, the circuit proposed in this paper reduce the maximum available gain by 1 dB, while conventional simple resistor circuit reduce it by 5.2 dB.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.173-176
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• 2006

This paper discusses the ZVS/ ZVZCS Three-Level converter using the minimum auxiliary circuit. A primary auxiliary circuit, which consists of one coupled inductor is added in the primary circuit to provide ZVZCS conditions to primary switches. ZVS is for outer switches and ZCS or ZVS is for inner switches. Many advantages including simple circuit topology high efficiency, and low cost make this converter attractive for high power applications. The principle of operation, feature and design considerations arc illustrated and verified through the experiment with a 2kHz 400kHz IGBT based experimental circuit.

• Proceedings of the KIEE Conference
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• 2005.04a
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• pp.134-139
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• 2005

This paper presents a cost effective quasi-resonant soft-switching PWM high frequency inverter with minimum circuit components. This inverter can achieve wider soft commutation, simpler power circuit configuration, smaller volumetric size, lower cost and wider power regulation range, higher-efficiency as compared with single ended quasi-resonant ZVS-PFM inverter and active voltage clamped quasi-resonant ZVS-PWM inverter. The operation principle of the proposed inverter is described on the basis of the simulation and experimental results, together with its operating performances in steady state. The operating performances of this unique proposed high frequency inverter based on ZVS and ZCS arms-related soft commutation principle is evaluated and discussed as compared with the active voltage-clamped ZVS-PWM inverter and a conventional single-ended ZVS-PFM inverter. The practical effectiveness of a novel type quasi-resonant soft-switching PWM high frequency inverter using IGBT is actually proved for consumer induction heated appliances as rice cooker, hot water producer, steamer and super heated steamer. The extended bidirectional circuit topology of quasi-resonant PWM high frequency inverter with minimum circuit components is demonstrated, which operate as the direct frequency changer.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.181-190
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• 2019

Active power decoupling circuits have emerged to eliminate the inherent second-order ripple power in a single-phase power conversion system. This study proposes a design method to determine the optimal capacitance for active power decoupling circuits to achieve high power density. Minimum capacitance is derived by analyzing ripple power in a passive power decoupling circuit, a buck-type circuit, and a capacitor-split-type circuit. Double-frequency ripple power decoupling capabilities are also analyzed in three decoupling circuits under a 3.3 kW load condition for a battery charger application. To verify the proposed design method, the performance of the three decoupling circuits with the derived minimum capacitance is compared and analyzed through the results of MATLAB -Simulink and hardware-in-the-loop simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.184-188
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• 2014

There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability ($V_{WL,OPT}=1.055V$) as well as to lower the minimum operating voltage for the read and write operations simultaneously ($V_{MIN,READ}=0.58V$, $V_{MIN,WRITE}=0.82V$ for supply voltage $(V_{DD})=1.1V$).

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1512-1515
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• 1987

The buffer circuit having minimum delay time is designed and analyzed in this paper. Considering the parasitic components of the MOS transistor, the optimal transistor size ratio between the individual buffer stages is presented. This paper's result is better than that of the Mead and Conway's analysis [1] with respect to both delay time and total area that buffer occupies.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.745-750
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• 2007

In this paper, we propose a new gate modification method using the input vector maximizes the number of gates in WLS within the optimum range of the minimum leakage power. We prove that MLV is not always the optimal solution, and that the leakage power and area can decrease when modifying the gates using the input vector for which the number of gates in WLS is maximized within the optimum range of the minimum leakage power for the circuits applying the IVC technique and gate modification method. Using the proposed method, the gate-level description circuit can be converted to the modified circuit which reduces the leakage power by chip designer, and the modified circuit can be applied without any modification in design flow.