JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array

  • Shin, Changhwan (School of Electrical and Computer Engineering, University of Seoul)
  • Received : 2013.05.16
  • Accepted : 2014.02.14
  • Published : 2014.04.30
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Abstract

There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability ($V_{WL,OPT}=1.055V$) as well as to lower the minimum operating voltage for the read and write operations simultaneously ($V_{MIN,READ}=0.58V$, $V_{MIN,WRITE}=0.82V$ for supply voltage $(V_{DD})=1.1V$).

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References

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