[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.5573/JSTS.2014.14.2.184

Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array

Shin, Changhwan (School of Electrical and Computer Engineering, University of Seoul)

Publication Information

JSTS:Journal of Semiconductor Technology and Science / v.14, no.2, 2014 , pp. 184-188 More about this Journal

Abstract

There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability ( $V_{WL,OPT}=1.055V$ ) as well as to lower the minimum operating voltage for the read and write operations simultaneously ( $V_{MIN,READ}=0.58V$ , $V_{MIN,WRITE}=0.82V$ for supply voltage $(V_{DD})=1.1V$ ).

Keywords

Variability; CMOS; SRAM;

Citations & Related Records

Reference

1	K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, and H. Shinohara, "A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment," VLSI Symp. on Circuit Digest, USA, pp. 212-213, June 2008.
2	C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sandford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, and K. Mistry, "A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors," VLSI Symp. on Tech. Digest, USA, pp. 131-132, June 2012.
3	E. Seevinck, F. J. List, and J. Lohstroh, "Staticnoise margin analysis of MOS SRAM cells," IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 748-754, October 1987. DOI
4	A. Carlson, Z. Guo, L.-T. Pang, T.-J. K. Liu, and B. Nikolic, "Compensation of systematic variations through optimal biasing of SRAM wordlines," IEEE Custom Integrated Circuits Conference, USA, pp. 411-413, September 2008.
5	Y. Fujimura, O. Hirabayashi, T. Sasaki, A. Suzuki, A. Kawasumi, Y. Takeyama, K. Kushida, G. Fukano, A. Katayama, Y. Niki, and T. Yabe, "A configurable SRAM with constant-negative-level write buffer for low-voltage operation with $0.149{\mu}m^2$ cell in 32nm high-k metal-gate CMOS," IEEE International Solid-State Circuits Conference, USA, pp. 348-349, February 2010.
6	H. Nho, P. Kolar, F. Hamzaoglu, Y. Wang, E. Karl, Y.-G. Ng, U. Bhattacharya, K. Zhang, "A 32nm high-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation," IEEE International Solid-State Circuits Conference, USA, pp. 346-347, February 2010.
7	M. Khellah, Y. Ye, N. S. Kim, D. Somasekhar, G. Pandya, A. Farhang, K. Zhang, C. Webb, and V. De, "Wordline & Bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65nm CMOS designs," VLSI Symp. on Circuit Digest, USA, pp. 9-10, June 2006.
8	M. Khellah, D. Khalil, D. Somasekhar, Y. Ismail, T. Karnik, and V. De, "Effect of power supply noise on SRAM dynamic stability," VLSI Symp. on Circuit Digest, USA, pp. 76-77, June 2007.
9	H. Pilo, I. Arsovski, K. Batson, G. Braceras, J. Gabric, R. Houle, S. Lamphier, F. Pavlik, A. Seferagic, L.-Y. Chen, S.-B. Ko, and C. Radens, "A 64Mb SRAM in 32nm high-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements," IEEE International Solid-State Circuits Conference, USA, pp. 254-256, February 2010.
10	M. E. Sinangil, H. Mair, A. P. Chandrakasan, "A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V," IEEE International Solid-State Circuits Conference, USA, pp. 260-262, February 2011.
11	E. Karl, Y. Wang, Y.-G. Ng, Z. Guo, F. Hamzaoglu, U. Bhattacharya, K. Zhang, K. Mistry, and M. Bohr, "A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active $V_{MIN}$ -enhancing assist circuitry," IEEE International Solid-State Circuits Conference, USA, pp. 230-232, February 2012.
12	Y. Wang, E. Karl, M. Meterelliyoz, F. Hamzaoglu, Y.-G. Ng, S. Ghosh, L. Wei, U. Bhattacharya, and K. Zhang, "Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6V 32nm LP SRAM," IEEE International Electron Devices Meeting, USA, pp. 32.1.1-32.1.4, December 2011.
13	O. Hirabayashi, A. Kawasumi, A. Suzuki, Y. Takeyama, K. Kushida, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, T. Nakazato, Y. Shizuki, N. Kushiyama, and T. Yabe, "A process-variationtolerant dual-power-supply SRAM with $0.179{\mu}m^2$ Cell in 40nm CMOS using level-programmable wordline driver," IEEE International Solid-State Circuits Conference, USA, pp. 458-459, February 2009.